This paper summarizes results from recent experiments which quantify the performance effects of multiple register sets on computer architectures 1.These experiments started with the simulation of procedure-intensive benchmarks on three different computer architectures which had various register set schemes added to them.The results from these simulations were dramatic, yet they were difficult to interpret since many interacting factors were involved.This led to a more focussed study to characterize the parameter passing and procedure context switching costs of various register set schemes.The basic hypothesis behind this work, that the performance gains from multiple register sets are independent of instruction set complexity, is supported by the results.Also of interest is the perspective this study gives on the interactions between parameter passing, procedure state saving, and machine architecture.