The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity.Added complexity increases the risks in achieving functionally correct first silicon.Existing design verification techniques were supplemented by applying emulation to obtain an early look at functionality.Discussed are the goals, methods and results of the UltraSPARC-I emulation.

The realization of a high performance modern microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be performed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b four-way superscalar processor, but more importantly it presents the analysis and tradeoffs that were made "en route" to the final chip. Among several issues, the in-order execution model is compared with alternatives, variations of the issue-width of the machine as well as the number of functional units are described, subtle features that are part of the memory hierarchy are explained, and the advantages of the packet-switched interconnect are exposed.