The performance of an interleaved common memory accessed uniformly by multiple processors is modeled by queuing and simulation methods. The model includes access conflicts at the bank level while assuming an ideal access network. A general scaling law is derived that indicates that memory access delays are given by the product of the bank reservation time and a function of the memory utilization, which is the average number of access requests arriving at a bank per bank reservation time. For light, uniform memory traffic. access delays are proportional to the square of the bank reservation time and to the ratio of the number of active memory access streams to the number of memory banks. With an assumption of random access patterns, an open and a closed queuing model are developed. To model pipelined access operations a new negative feedback model is introduced that includes the open and the closed models as special cases and is also well suited for modeling linked access streams. Delay dependence on bank reservation time is quadratic for light loads and linear for very heavy loads. The queuing models are validated by simulations.>

The delay of accesses in shared-memory vector multiprocessors is considered. Simple formulae are presented which predict the delays of both scalar and vector accesses with a variety of loads in terms of memory technology and design parameters. Comparisons are made with both simulated and measured results on five CRAY memory systems.

A performance study is made of dynamic and static memory versions of the CRAY-2. This includes comparative kernel-level performance as well as direct measurement of memory accessing delays. A “black-box” memory accessing model is proposed and the results of preliminary tests on this model are given. Open questions in relating memory characteristics and code performance are reviewed.

In a multiport memory access vector processor such as the CRAY X-MP, the numbering of section (lines) relative to bank numbering affects the delay characteristics of vector memory accesses. The author examines numberings which affect the vector startup delay. It has been shown previously that section numberings now associated with the X-MP-4 reduced the steady-state section delays of randomly conflicting vector accesses, vis-a-vis the X-MP-2 numberings. For the present study, it is shown that these same numberings increase the startup delays of such accesses, thus establishing a tradeoff between numbering protocols.>