We propose a compression method for True Random Bit Generators (TRBGs) that exploits pseudo-chaotic systems. The compression scheme requires extremely low-complex hardware circuits for being implemented whereas its theoretical explanation is based on a weaker and more general interpretation of the Shadowing Theory, focusing on probability measures, rather than on single chaotic trajectories. We prove theoretically how to design the overall compression scheme, in order to assure the final entropy of the compressed TRBG to be arbitrarily close to the maximum theoretical limit of 1 bit/time-step.

In this paper, a general model of multibit Differential Power Analysis (DPA) attacks to precharged buses is discussed, with emphasis on symmetric-key cryptographic algorithms. Analysis provides a deeper insight into the dependence of the DPA effectiveness (i.e., the vulnerability of cryptographic chips) on the parameters that define the attack, the algorithm, and the processor architecture in which the latter is implemented. To this aim, the main parameters that are of interest in practical DPA attacks are analytically derived under appropriate approximations, and a novel figure of merit to measure the DPA effectiveness of multibit attacks is proposed. This figure of merit allows for identifying conditions that maximize the effectiveness of DPA attacks, i.e., conditions under which a cryptographic chip should be tested to assess its robustness. Several interesting properties of DPA attacks are derived, and suggestions to design algorithms and circuits with higher robustness against DPA are given. The proposed model is validated in the case of DES and AES algorithms with both simulations on an MIPS32 architecture and measurements on an FPGA-based implementation of AES. The model accuracy is shown to be adequate, as the resulting error is always lower than 10 percent and typically of a few percentage points.

This paper discusses a general model of differential power analysis (DPA) attacks to static logic circuits. Focusing on symmetric-key cryptographic algorithms, the proposed analysis provides a deeper insight into the vulnerability of cryptographic circuits. The main parameters that are of interest in practical DPA attacks are derived under suitable approximations, and a new figure of merit to measure the DPA effectiveness is proposed. Worst case conditions under which a cryptographic circuit should be tested to evaluate its robustness against DPA attacks are identified and analyzed. Several interesting properties of DPA attacks are also derived from the proposed model, whose fundamental expressions are compared with the counterparts of correlation power analysis attacks. The model was validated by means of DPA attacks on an FPGA implementation of the advanced encryption standard algorithm. Experimental results show that the model has a good accuracy, as its error is always lower than 2%.

In this paper an efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps is proposed. As an application example, the method is used to evaluate for a chaos-based true random bit generator the robustness of the entropy with respect to small map parameters variations.

In this paper, fully digital True Random Bit Generators (TRBGs) targeting area-efficient FPGA implementations are analyzed and evaluated. In this analysis, a very general class of TRBGs is considered that is based on the well-known sampling oscillators used as a building block. A qualitative model is discussed and applied to derive simple design guidelines to implement low-area TRBGs. Extensive measurements are made on TRBGs implemented on Altera Cyclone FPGAs. Results confirm that properly designed TRBGs based on FPGAs can achieve very high-quality random sequences with low area occupation.

In this paper, a general model of multi-bit differential power analysis (DPA) attacks to static logic circuits is proposed, with emphasis on symmetric-key cryptographic algorithms. The main parameters that are of interest in practical DPA attacks are analytically derived by introducing suitable approximations. Several interesting properties of DPA attacks are derived, allowing a deep understanding of the vulnerability of algorithms and circuits. The proposed model was validated by means of experimental measurements on an FPGA implementation of the Advanced Encryption Standard (AES) algorithm. The model accuracy is shown to be adequate, as the resulting error is always lower than 11%.

In this paper a novel family of maximum-period nonlinear congruential generators (NLCGs) based on the digitized sawtooth map is considered for the definition of hardware and software efficient pseudo random number generators (PRNGs). A list of such maximum period NLCGs for period lengths up to 231-1 is provided. Referring to the NIST800-22 statistical test suite, a PRNG example based on the combination of two of the proposed NLCGs is presented and discussed

In this paper, techniques to improve the resistance against differential power analysis (DPA) attacks of precharged busses in cryptographic circuits are discussed. In particular, two techniques that were previously introduced by the same authors are properly mixed to further enhance the immunity to DPA attacks. The achieved robustness against DPA attacks is shown to be considerably improved, compared with the case of a separate adoption of each technique. Criteria to manage the security-power-area trade-off are also derived from a statistical analysis of precharged busses. The mixed technique is finally validated by means of both cycle-accurate and circuit simulations on the DES encryption algorithm running on a MIPS32 architecture.

In this paper the theoretical bases to design a true random bit generator (TRBG) circuit with a predefined minimum entropy are discussed. The approach is tailored to TRBGs based on a one-dimensional piecewise-linear chaotic map, and it is based on a feedback control procedure that allows to dynamically changing the system parameters. For this purpose, the procedure just exploits the TRBG output observation without requiring bit throughput reduction. The design approach was validated by an hardware prototype implemented on a field programmable analog array (FPAA)

In this paper, hysteresis is exploited to improve the performance of positive feedback source coupled logic circuits, which are a modification of the traditional MOS current-mode logic (MCML) (Alioto, 2004). To understand the effect of hysteresis on the DC characteristics, a model of the noise margin is analytically derived. This model shows that hysteresis improves the noise margin, whose increase is traded-off to reduce the logic swing, which in turn can have a beneficial impact on the speed performance. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Analysis shows that in such cases hysteresis significantly improves the speed performance and the power efficiency of PFSCL gates, which is a critical aspect in this kind of logic. Simulation results are presented based on a 0.18-mum CMOS process

In this paper an ultrasonic multisensor acquisition and processing system with up to 32 air-ultrasound transducers in the frequency range of 40-200 kHz is presented. The system was developed for an obstacle avoidance applications in the robotics field. The acquisition and processing capability of the equipment (based on the digital signal processor TMS320C25 and can sample up to five parallel channels) allows the robot to perform tasks of different difficulty levels, from target-ranging to pattern recognition. As an example of application, a neural approach to a typical problem in the robotic navigation field is presented, which highlights the system-flexibility features.

The authors present a multi-DSP (digital signal processing) system based on commercial chips. The structure is a MIMD (multiple-instruction multiple-data) machine with a data-driven organization. A locally parallel link based on a memory shared between two adjacent nodes assures the asynchronous exchange of data. The system is also characterized by a global serial channel useful for program-loading purposes and noncritical data paths. A mathematical model is used to evaluate the performance of the multi-DSP system. The apparatus is used in ultrasound Doppler parameter estimation but the processing architecture is suitable for general real-time applications.>