The reliability of LDMOSFET as well as FinFET devices has been gaining much interest in the development of various space electronic systems. There are high requirements for nonlinear computation and efficient simulation of radiation-multiphysics effects in these devices, especially in large-scale 3D scenarios, which pose significant challenges. To address these issues, we propose a hybrid numerical method for massively parallel simulation of nonlinear drift-diffusion transport processes in semiconductor devices. The control volume finite element method (CV-FEM) is employed to solve the Poisson, current continuity, and heat conduction equations, which shows strong numerical stability on unstructured meshes compared with the commercial COMSOL Multiphysics software. Further, our self-developed solver is employed to explore the total ionizing dose (TID)-electrothermal synergistic effects in step-doped LDMOSFETs (SD-LDMOSFETs), high-K dielectric SD-LDMOSFETs (HKSD-LDMOSFETs), and multi-fin FinFETs (M-FinFETs). We also implement a combined domain decomposition and J parallel Adaptive Unstructured Mesh applications Infrastructure scheme for parallel computation, where the scalability of our parallel algorithm is examined. It it believed that this study can offer some new insights into the behavior of these devices under radiation and electrothermal coupling, advancing efficient numerical methods to simulate diverse radiation-electrothermal synergistic effects.

With the rapid development of IoT technology in recent years, higher requirements have been put forward for wireless communication technology. Low Power Wide Area Network (LPWAN) technology is emerging rapidly, the technology is characterized by low power consumption, low bandwidth, long-distance, and a large number of connections, and is specifically designed for Internet of Things applications. LoRa (Low Power Long Range Transceiver), as a typical representative of LPWAN technology, has been widely concerned and studied. This paper analyzes the performance of LoRa modulation in the tree topology network and analyzes the performance of LoRa modulation in the imperfect environment for point-to-point communication and multipoint-to-point communication. From theoretical analysis and performance simulation, it can be seen that the influence of frequency offset or multipath fading on LoRa signal is very obvious. However, when LoRa modulation is used for networking, multi-user interference will be introduced. Under the influence of many imperfect factors, the signal receiver performance of LoRa modulation will be difficult to guarantee. Because of these effects, Coordinated Multiple Points based on Timing Delay (DCoMP) is presented. Multiple nodes close to each other send the same data to the target node. Due to the inaccurate synchronization between nodes, there will be a certain relative delay when sending signals to the same target node. After the receiving node combines the signals of multiple nodes according to different relative delays, the reception performance of the signals can be improved. At the same time, the cooperative node can also actively adjust the signal sending time to improve the reception performance of the receiving node signal merging algorithm. LoRa modulation, by using DCoMP transmission, improves the reception of signals and thus the overall capacity of the system. Through the analysis of multipoint communication and single point communication, this paper is of great help to LoRa network deployment.

Secure masking schemes have been proven in theory to be secure countermeasures against side-channel attacks. The security framework proposed by Ishai, Sahai and Wagner, known as the Ishai-Sahai-Wagner scheme, is one of the most acceptable secure models of the existing dth-order masking schemes, where d represents the masking order and plays the role of a security parameter. However, a gap may exist between scheme and design. Several analyses have determined that the glitch has been regarded as the main challenge of masking in hardware designs. A practical method of locating the precise position of leakage points (LPs) in the original hardware design is very rare. Existing research on this glitch mainly focuses on the first-order leakages; however, higher-order analysis can combine several shares to recover the secret key. In this paper, we propose a practical method, sensitive glitch location (SGL) method to locate the less order leakage in hardware design. Specifically, the SGL method can locate any-order of LP in the hardware implementation of dth-order masking schemes. We conducted experiments and verified that the time complexity of SGL on the dth-order masking schemes is O(nm), where m is the number of signals and n is the number of shares in masking scheme. It can therefore be regarded as an efficient tool for the masking designs. In addition, we analyzed the dth-order masking scheme proposed by Rivain and Prouff (2010) along with the SecMult algorithm from the Rivain-Prouff countermeasure, which has been analyzed by our SGL. The experimental results verified that a higher-order leakage may exist in certain hardware designs, even the masking scheme has been proven as a secure countermeasure. To the best of our knowledge, SGL is the first tool that can be used to locate any-order of power/electromagnetic LP in hardware designs. It thus shows the weakness in the original design file of hardware implementations. This property can help designers directly improve the real security of the designs. Moreover, SGL returns the path of the leakages, which can elucidate the original cause and propagation of the weakness.