Simulations of biological tissue have been extensively used to replicate phenomena observed by in-vivo and in-vitro experiments as an alternative methodology for explaining how computations could take place in a brain region. Additional benefits of simulated neural networks over in-vivo experiments include greater observability, experimental control and reproducibility. General-purpose supercomputers provide the computational power and parallelism required to implement highly complex neural models, but this comes at the expense of high power requirements and communication overheads. Moreover, there are certain cases where real-time simulation performance is a desirable feature, for example in the field of cognitive robotics where embodied agents need to interact with their environment through biologically inspired asynchronous sensors. The SpiNNaker neuromimetic platform is a scalable architecture that has been designed to enable energy-efficient, large-scale simulations of spiking neurons in biological realtime. This work is based on a recent study which revealed that while they are generally energy efficient, SpiNNaker chips dissipate significant amount of power whilst in the idle state. In this paper we perform a systematic investigation into the overall energy consumption of a SpiNNaker system and propose a number of optimised suspend modes in order to reduce this. The proposed implementation is 60% more energy efficient in the idle state, 50% in the uploading and 52% in the downloading phases, while the power dissipation of the whole simulation is reduced by 52%. For demonstration purposes, we run a neural network simulation comprising thousands of neurons and millions of complex synapses on a 48-chip SpiNNaker board, generating millions of synaptic events per second.

When two or more sound detectors are available, interaural time differences may be used to determine the direction of a sound's origin. This process, known as sound localization, is performed in mammals via the auditory pathways of the head and by computation in the brain. The Jeffress Model successfully describes the mechanism by exploiting coincidence detector neurons in conjunction with delay lines. However, one of the difficulties of using this model on neural simulators is that it requires timing accuracies which are much finer than the typical 1 ms resolution provided by simulation platforms. One solution is clearly to reduce the simulation's time step, but in this paper we also explore the use of population coding to represent more precise timing information without changing the simulation's timing resolution. The implementation of both the Jeffress and population coded models are contrasted, together with their results, which show that population coding is indeed able to provide successful sound localization.

Simulating large spiking neural networks is non trivial: supercomputers offer great flexibility at the price of power and communication overheads; custom neuromorphic circuits are more power efficient but less flexible; while alternative approaches based on GPGPUs and FPGAs, whilst being more readily available, show similar model specialization. As well as efficiency and flexibility, real time simulation is a desirable neural network characteristic, for example in cognitive robotics where embodied agents interact with the environment using low-power, event-based neuromorphic sensors. The SpiNNaker neuromimetic architecture has been designed to address these requirements, simulating large-scale heterogeneous models of spiking neurons in real-time, offering a unique combination of flexibility, scalability and power efficiency. In this work a 48-chip board is utilised to generate a SpiNNaker power estimation model, based on numbers of neurons, synapses and their firing rates. In addition, we demonstrate simulations capable of handling up to a quarter of a million neurons, 81 million synapses and 1.8 billion synaptic events per second, with the most complex simulations consuming less than 1 Watt per SpiNNaker chip.

SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 105 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected.

One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker.

As models of neural networks scale in concert with increasing computational performance, gaining insight into their operation becomes increasingly important. This paper proposes an efficient and generalised method to access simulation data via in-system aggregation, providing visualised representation at all layers of the network in real-time. Enabling neural networks for real-time visualisation allows a user to gain insight into the network dynamics of their systems as they operate over time. This visibility also permits users (or a computational agent) to determine whether early intervention is required to adjust parameters, or even to terminate operation of experimental networks that are not operating correctly. Conventionally the determination of correctness would occur post-simulation, so with sufficient `in-flight' insight, a significant advantage may be obtained, and compute time minimised. For this paper we apply the real-time visualisation platform to the SpiNNaker programmable neuromimetic system and a variety of neural network models. The visualisation platform is shown to be capable across a range of diverse simulations, and at supporting differing layers of network abstraction, requiring minimal configuration to represent each model. The resulting general-purpose visualisation platform for neural networks, is effective at presenting data to users in order to aid their comprehension of the network dynamics during operation, and scales from small to biologically-significant network sizes.

SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically plausible spiking neural networks in real-time. A SpiNNaker machine consists of up to 216homogeneous eighteen-core multiprocessor chips, each with an on-board router which forms links with neighbouring chips for packet-switched interprocessor communications. The architecture is designed for dynamic reconfiguration and optimised for transmission of neural activity data, which presents a challenge for machine configuration, program loading and simulation monitoring given a lack of globally-shared memory resources, intrinsic addressing mode or sideband configuration channel. We propose distributed software mechanisms to address these problems and present experiments which demonstrate the necessity of this approach in contrast to centralised mechanisms.

This paper presents the algorithm and software developed for parallel simulation of spiking neural networks on multiple SpiNNaker universal neuromorphic chips. It not only describes approaches to simulating neural network models, such as dynamics, neural representations, and synaptic delays, but also presents the software design of loading a neural application and initial a simulation on the multi-chip SpiNNaker system. A series of sub-issues are also investigated, such as neuron-processor allocation, synapses distribution, and route planning. The platform is verified by running spiking neural applications on both the SoC Designer model and the physical SpiNNaker Test Chip. This work sums the problems we have solved and highlights those requiring further investigations, and therefore it forms the foundation of the software design on SpiNNaker, leading the future development towards a universal platform for real-time simulations of extreme large-scale neural systems.

A JBits implementation of the Data Encryption Standard (DES) algorithm in a Virtex FPGA is described. The Virtex architecture efficiently implements the DES primitive operations, and permits a high degree of pipelining. JBits provides a Java-based Application Programming Interface (API) for the run-time creation and modification of the configuration bitstream. This allows dynamic circuit specialization based on a specific key and mode (encrypt or decrypt). The key schedule is computed entirely in software, and is part of the bitstream. As a result, all cryptographic key input and subkey generation logic are removed from the fully unrolled datapath. When combined with a speed efficient layout the result is a throughput of over 10 Gigabits per second. This exceeds the performance of a recently announced DES ASIC.

Today's FPGAs are no longer used simply for glue logic. They possess sufficient gate capacity and performance to implement intellectual property (IF) blocks and other complex systems consisting of data paths, control logic, I/O, and memories. System-on-chip designers who target FPGAs are increasingly turning towards reusable IP libraries as a means of coping with increased design complexity. Unfortunately, creating libraries of parametric IP for FPGAs is an arduous task. Despite improvements in algorithmic mapping, placement, and routing, high-performance FPGA circuits often require hand-crafted layout. The design problem is further complicated by the requirement that hand-crafted IP target multiple FPGA families. We have developed a method of floorplan specification and evaluation that greatly simplifies the design of such hand-crafted parametric IP. Template-based placement directives are used to specify layout in abstract coordinates that are independent of the sizes of placed components. They provide powerful abstractions for specifying complex geometric relations, and are particularly well-suited to structured circuits that require custom floorplanning to achieve high performance or density. It should be emphasized that for such circuits, all current algorithmic approaches are inadequate. Placement directives relieve the designer of unnecessary tedium by automating the translation from an abstract geometric specification into low-level device coordinates. Although this approach to automation is not new, it is perhaps underappreciated. Superior descriptive abstraction provides substantial benefit in the creation, maintenance, and reuse of hand-crafted parametric IP.

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