AI-based frameworks for protein engineering use self-supervised learning (SSL) to obtain representations for downstream mutation effect predictions. The most common training objective for these methods is wildtype accuracy: given a sequence or structure where a wildtype residue has been masked, predict the missing amino acid. Wildtype accuracy, however, does not align with the primary goal of protein engineering, which is to suggest a mutation rather than to identify what already appears in nature. Here we present Evolutionary Ranking (EvoRank), a training objective that incorporates evolutionary information derived from multiple sequence alignments (MSAs) to learn more diverse protein representations. EvoRank corresponds to ranking amino-acid likelihoods in the probability distribution induced by an MSA. This objective forces models to learn the underlying evolutionary dynamics of a protein. Across a variety of phenotypes and datasets, we demonstrate that EvoRank leads to dramatic improvements in zero-shot performance and can compete with models fine-tuned on experimental data. This is particularly important in protein engineering, where it is expensive to obtain data for fine-tuning.

As Multichip Modules (MCMs) evolve from niche solutions to necessary ingredients of high performance computing systems, this change must be reflected in the associated CAD tools for MCM system design. Given the transmission velocities of modern thin film substrates, conventional design techniques where chips are developed in isolation from the substrate fall short of producing optimal solutions. Critical to the success of these tools is the ability to influence chip pad placement. Our research indicates that an integrated chip/MCM codesign environment should be established. MCM CAD tools must provide advice for and accommodate an interactive pad migration facility, where chip designers are provided recommended signal pad locations that contribute to the optimization of the overall system.

The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database.>

MCM designs require independent analysis in loosely coupled but interrelated design regimes. This paper proposes wiring pitch as the unifying thread in a real time iterative design environment that facilitates analysis in all pertinent domains. Actual system results demonstrate the strengths of the technique.>

Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a 1-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology and triple-level full-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (/spl les/10 GHz) and high-density (/spl les/40 /spl mu/m pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2.0/spl times/10/sup 5/ W/m/sup 2/. Poor heat conduction ability of GaAs chips make it tough to dissipate this hear. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented.>

Recently published findings indicate that full differential routing of both VLSI chips and MCMs may be necessary to preserve noise margins in high performance systems. The optimal differential routing technique relies on routing signal pairs as logical nets and bifurcating the results to achieve a physical realization. Based on our research, CIF (Caltech. Interchange Format) has emerged as the ideal medium for the bifurcation process associated with differential routing of MCMs. Since MCMs have not as yet fully come of age, many of their design variables are under constrained. One of the greatest strengths of our finding is CIF's ability to handle the design uncertainty associated with current MCM system development, where both package and chip specification are typically in a tremendous state of flux throughout the engineering design cycle.>

A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps.>