Demo Data from SIGIR 2026 / reviewers in the wild / expert
Frank H. Hielscher
dblp:64/4921
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › high-level synthesis
data path synthesis |
0.0 | 1 | 1995 | Datapath synthesis using a problem-space genetic algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation
high-level synthesis |
0.0 | 1 | 1995 | Datapath synthesis using a problem-space genetic algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation › high-level synthesis
scheduling and allocation |
0.0 | 1 | 1995 | Datapath synthesis using a problem-space genetic algorithm · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Methods — techniques the papers use, named apart from their topics
heuristic search · 0.0genetic algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | Datapath synthesis using a problem-space genetic algorithmabstractThis paper presents a new approach to datapath synthesis based on a problem-space genetic algorithm (PSGA). The proposed technique performs concurrent scheduling and allocation of functional units, registers, and multiplexers with the objective of finding both a schedule and an allocation which minimizes the cost function of the hardware resources and the total time of execution. The problem-space genetic algorithm based datapath synthesis system (PSGA-Synth) combines a standard genetic algorithm with a known heuristic to search the large design space in an intelligent manner. PSGA-Synth handles multicycle functional units, structural pipelining, conditional code and loops, and provides a mechanism to specify lower and upper bounds on the number of control steps. The PSGA-Synth was tested on a set of problems selected from the literature, as well as larger problems created by us, with promising results. PSGA-Synth not only finds the best known results for all the test problems examined in a relatively small amount of CPU time, but also has the ability to efficiently handle large problems.> Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1985 | Backdrive Stress-Testing of CMOS Gate Array Circuits
Frank H. Hielscher, John C. Pagano |
ITC | 1 |