An extended correlation operation is proposed to construct odd-length Z-complementary code sets (ZCCSs) and complete complementary codes (CCCs) with new parameters. The construction helps to extend the code capacity of ZCCSs and CCCs. In the majority of published works, the length of CCCs is more than or equal to the number of complementary codes and the length of the code expands rapidly as the code capacity increases. This study has the advantage of a considerably increased number of complementary codes and a very minor increase in code length. Increasing the number of codes can expand the system capacity, and short sequence length can improve the system transmission efficiency, so the constructed code sets may be applicable to high-capacity wireless communication systems. Furthermore, ZCCSs and CCCs can minimize multiple-access interference (MAI) and multi-path interference (MPI) due to excellent correlation property.

Coherent joint transmission (JT), where multiple transmitters send a common message with phase constructively combined at a receiver, is a promising technique to improve the signal power and spatial diversity in 5G networks. In this paper, we reconsider the two-way and master-slave synchronization protocol for coherent JT taking into account the impact of different response of transmit/receive chains. Measurement results and system level simulations for coherent JT are provided. The results show that coherent JT provides significant throughput gains compared with other coordination schemes.

In this paper, a novel depth ordering inference approach is presented. Our main insight is to integrate the discriminative feature selection, occlusion feature learning and same-layer (S-L) relationship judgement into a uniform sparsity based classification objective, which cannot only supply the precise segmentation for the occlusion edge, but also reduce the solution space for the depth ordering inference efficiently. In addition, a novel triple descriptor is adopted to judge the foreground relationship, which is more discriminative than conversional local cues and can further reduce the solution space. The inference is executed by finding a valid path on a directed graph model. We validate our approach on the Cornell depth-order dataset and the NYU 2 dataset, and the convincing experimental results demonstrate the effectiveness of our approach.

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is < 4% at all corners.

In nanometer technologies, process variations possess growing nonlinear impacts on circuit performance, which causes critical path delays of combinatorial circuits variate randomly with non-Gaussian distribution. In this paper, we propose a novel clock skew scheduling methodology that optimizes timing yield by handling non-Gaussian distributions of critical path delays. Firstly a general formulation of the optimization problem is proposed, which covers most of the previous formulations and indicates their limitations with statistical interpretations. Then a generalized minimum balancing algorithm is proposed for effectively solving the skew scheduling problem. Experimental results show that the proposed method significantly outperforms some representative methods previously proposed for yield optimization, and could obtain timing yield improvements up to 33.6% and averagely 17.7%.

Deep Packet Inspection (DPI) is a critical function in network security applications such as Firewalls and Intrusion Detection Systems (IDS). Signature based scanners used in DPI apply multi-pattern matching algorithms to check whether the packet payload or flow content contains a specified signature in a signature set. Existing multi-pattern matching algorithms sacrifice memory space to achieve better performance. In this paper a novel fast multi-pattern matching algorithm, the Hash Boyer-Moore (HBM) Algorithm, is presented, which reduces the memory footprint of the heuristic table using a hash function and adds another heuristic table to reduce the false-positive ratio. Analyses and simulations show HBM offers higher speed and lower memory cost than some existing algorithms. The HBM algorithm was implemented on the Intel IXP 2400 Network Processor (NP) platform and experiments show suitable performance results in a Gigabit Ethernet LAN environment.

In this paper, an AntiWorm system based on the Intel IXP Network Processor was implemented using the Parallel Bloom filters technique. The AntiWorm system consists of two components: Bloom filters and Exact Matching engines. The Parallel Bloom filters can identify the suspicious traffic quickly and effectively, and then dispatch them to Exact Matching engines for further investigation. Both the principles and the implementation of the AntiWorm system are introduced in detail. With the consideration of the system performance parameters, two feasible implementation solutions are investigated and the advantages and disadvantages are also compared. The selections of configuration parameters of the AntiWorm system are also discussed. A hash scheme based on MD5's function is proposed for implementing fast hash functions. To test the performance of the AntiWorm system, such as throughput and delay, some experiments are carried out with different simulated traffic condition. The internal statistics of IXP network processor are also collected and analyzed for optimizing the system performance. To demonstrate the operation of the AntiWorm system, assaults by Worm Blaster are used in the test bed, and the experimental results prove the effectiveness of the AntiWorm system. The Software Package WormDetector1.0 is also provided as a software release from the research.

TCP/IP protocol suite carries most application data in Internet. TCP flow retrieval has more security meanings than the IP packet payload. Hence, monitoring the TCP flow has more strength than only monitoring the IP packet payload in the AntiWorm system. The main idea of this paper is to use the flexibility and high performance of network processors to scan TCP flow for locating worm's binary codes, and cut off their propagation. A stateful TCP flow inspection engine is implemented based on IXP network processor, which can monitor about 512K flows. The performance issues about IXP network processors are evaluated and collected, and an analysis is made for further optimizing the system performance. The system is also demonstrated and proved by using the Internet traces and real assaults of Worms. Software Package TCPScanner 1.0 is also given as a software release of the research