The author describes Fasolt, a system that automatically optimizes the bus topology of a register-level data-path design. The unique aspect of Fasolt is that it uses information taken from a detailed layout model to choose optimizing transformations of the bus topology and the schedule of operations and transfers of an existing design. Such a system is called a feedback-drive system because it uses information derived at a low level (in this case, that of physical layout) to drive the selection of optimizing transformations at a higher level or levels (in this case, the scheduling and allocation levels). This allows the scheduling and topology synthesis steps to take wiring considerations into account in a way that has hitherto not been demonstrated in an automatic synthesis system. Experiments have shown that improvements in area, cycle time, and overall average delay can often be achieved in the same design using this approach.>

The authors present a formal representation for register-level digital designs. The formalism is expressed in term of three models of a design, the data-flow structure, and timing models, and by bindings that express the interrelationships of the three models. The authors describe the desiderata that led to the particular choice of representation: a uniform representation for specification and implementation, the ability to express detailed implementation constraints, formality, descriptiveness, ease of testing, ease of encoding, executability, and prescriptiveness. They then describe related work and describe the representation and correctness constraints. Formal semantics for the representation are given, and a brief overview of a system that implements them is presented.>

A novel paradigm for managing the digital process is presented. Under this paradigm, design is seen as a process in which abstract models of design tools are applied to abstract models of design states in a simulated or planning space, until a sequence of design tasks has been constructed to completion. Important parameters of the hypothetical design represented by the terminal states are then estimated. Either the planning is then repeated, or the sequence, or plan, is then executed, or carried out, in an execution space. This execution is monitored for violation of expectations; if violations occur, control is returned to the planner. The knowledge base of the planner is populated with register-transfer level (RTL) concepts for digital system design; it can also be populated with other knowledge sets. The planner forms part of the USC advanced design automation (ADAM) system.>

The growing complexity of VLSI designs has led to a partitioning of design responsibilities among different engineers, with the result that engineers work in parallel on different aspects of the design. With this division of responsibilities comes the need for automatic means of coordinating changes made by different engineers, and automatic means of administrating design policies laid down by management. In this paper we show how an information-rich design environment, incorporating (1) detailed knowledge of the design, (2) explicit representation of management's policies, and (3) special software units called change coordinators, can be used to automate the functions of change coordination and policy administration.

A description is given of new capabilities of the RLEXT register level exploration tool. RLEXT is an interactive tool that takes a datapath design and allows a user to modify it freely, using transformations that do not themselves preserve correctness. By maintaining a representation of the desired behavior and timing as well as structure, RLEXT is able to 'repair' the design when the user creases modifying, so that the ability of the design to express the specified behavior is once again guaranteed. A description is also given of RLEXT's support for manual changes of schedule in the presence of an existing data-path structure. Such schedule changes invalidate the structure, but the structure is incrementally repaired rather than just thrown out. The author knows of no other high-level synthesis tool that supports this kind of functionality.>