The promising features introduced by the integration of ferroelectric devices into conventional integrated circuit fabrication processes have spurred extensive research into device reliability, non-volatile memory circuits and system-level applicability. Their low-power operation makes them particularly suitable for Internet of Things applications, and their intrinsic memory properties position them as strong candidates for nonvolatile memory technologies and In-memory Computing. For such data-intensive applications, the need to ensure secure data storage, processing and transmission has motivated the adaptation of classic hardware security strategies to this emerging inmemory computing paradigm, demonstrating high effectiveness with ferroelectric designs. However, a variability analysis from a design perspective remains unexplored towards either implementing security primitives based on identity, e.g. Physical Unclonable Functions, or based on stochasticity, e.g. True Random Number Generators.In this work, we focus on the variations expected in a commercial 28 nm process and its compatibility with memory cell design, in view of the implementation of a Physical Unclonable Function in a ferroelectric memory array. In particular we show that while obtaining a sufficient output variability, which can be used for fingerprinting the device, a fair current ratio is maintained, allowing memory array implementations.

Data-centric applications such as Artificial Intelligence and IoT are putting stringent performance and energy efficiency constraints on hardware implementations of computing architectures. Computing in Memory paradigm appears as a viable approach to to address such constraints and ferroelectric FETs (FeFETs) push this paradigm at a finer grain by enabling the design of true non-volatile logic gates, by implementing tight combination of memory and logic called Logic-in-Memory (LiM). From the basic non-volatile logic gate design up to the application-level evaluation, several challenges have to be addressed.In this paper, we present a methodology to design complex operations such as cryptographic operations using FeFET, integrate them into a complete computing architecture and evaluate its benefits. Current challenges related to logic synthesis and tools for synthesis of these LiM structures will also be discussed.

This paper describes the design of the wireless sensor network node (WSN) for distributed active vibration control (AVC) system for the automotive application.The approach of the system is presented in details.A WSN node using one piezoelectric element provides several features (sensing, shunting and energy harvesting).Integration of the vibration sensing capability for active vibration control system with the energy harvesting capability is described here.Simulation results are compared with the prototype design.

This paper presents IDEA1, a validated SystemC-based simulator for WSNs. It allows the system-level performance evaluation (e.g., packet transmission and energy consumption) with elaborate models of sensor nodes. IDEA1 uses a clock-based synchronization mechanism to support simulations with cycle accurate communication and approximate time computation. Its accuracy has been validated by a testbed of 9 nodes. The average deviation between the IDEA1 simulations and experimental measurements is 5.9%. The performances of IDEA1 have also been compared with NS-2, one of the most widely used simulators in WSN research. To provide a similar result (deviation less than 5%) at the same abstraction level, the simulation of IDEA1 is 2 times faster than NS-2. Moreover, with the hardware and software co-simulation feature, IDEA1 provides more detailed modeling of sensor nodes than NS-2.

This paper presents a complete SystemC-based Wireless Sensor Network model. It implements the entire IEEE 802.15.4 standard, and permits to simulate scenarios at high level, taking hardware and software low level parameters into account, also enabling design space exploration for system level designers.

6-8 July 2014

This paper describes a dynamically reconfigurable 8-function logic gate (CNT-DR8F) based on a double-gate carbon nanotube field effect transistor (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Using available models, CNT-DR8F is proposed, simulated and analyzed at 20 GHz operation. We also give an example functional block (full adder) to show how to construct logic circuits based on the association of physically identical reconfigurable logic cells.