Everybody agrees that curing DFM/DFY issues is of paramount importance at 65 nanometers and beyond. Unfortunately, there is disagreement about how and when to cure them. "Surgeons" suggest a GDSII-centered approach, potentially invasive, while "family doctors" recommend a more pervasive approach, starting from RTL. As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks. This panel examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad cross-section of semiconductor industry. Although there is general agreement among the panelists that both approaches are necessary and that prevention is the best way to proceed, they also acknowledge that the surgery may be unavoidable in such "hazardous" conditions as state-of-the-art technologies. However, as always, "the devil is in the details", and the diverse approaches to DFM presented below should make this panel quite interesting. We are also counting on the feedback from the IC design community to assess if these approaches are sufficient and practical enough to deal with the "health hazards". We are looking forward to an exciting discussion that will challenge our esteemed panelists

No abstract available.

For sub-100nm processes, predictions are putting initial process yields in the single digits. At the same time, at 130nm, we saw that two chips designed with the same methodology and same design rules could deliver completely different manufacturing yields.This panel will discuss the reasons for these phenomena and talk about future trends in DFM that will need to be addressed for success below 100nm.

In this paper we present an innovative methodology to estimate and improve the quality of analog and mixed-signal circuit testing. We first detect and reduce the redundancy in the electrical test measurements (e-tests), then we identify the e-test acceptability regions by considering performance specifications as well as process parameter distributions. Finally, we provide an effective metric for the accurate assessment of the parametric test coverage of embedded analog IP. Experimental results confirm the validity of the proposed methodology and its broad applicability to analog, mixed-signal and RF applications for different process technologies.

This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circuits. The main feature of this methodology is that it accounts for device mismatch by using a number of variables that is asymptotically constant in the limit of perfectly matching devices, and is typically close to the number of independent process factors normally used to account for inter-die process variations only. A unified model of process variation allows the effects of each source of variation and their joint impact to be estimated, thus providing designers more accurate analysis and variance optimization capability. State-of-the-art application examples demonstrate the accuracy and efficiency of this approach.

Abstract: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of abstraction. Only those components that are activated by a given input vector are added to the detailed simulation netlist. The methodology is suitable for parallel implementation on a multi-processor environment and allows to arbitrarily switch between fast and detailed levels of abstraction during the simulation run. The experimental results obtained on a significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory occupation together with a considerable degree of accuracy. Furthermore the proposed technique easily fits in the existing industrial design flows.

A new fast and accurate methodology for crosstalk analysis of large VLSI IC interconnects is presented. In the proposed approach a reduced order approximation of the original interconnect network is derived by using a general application of the moment matching technique. Subsequently, a macromodel of the crosstalk voltage in the time domain is obtained, and a general method for a precise evaluation of the crosstalk voltage peak is described. Finally, the macromodel is used in order to evaluate the delay caused by crosstalk effects. The methodology described has been implemented in a sign-off tool that can be effectively used to evaluate crosstalk effects in signal integrity analysis of large digital circuits. Potentially hazardous circuit behavior caused by crosstalk can thus be detected without running massive time consuming circuit simulations. The effectiveness of our approach is demonstrated by application examples.

An automatic modeling technique is presented in this paper that allows to build an accurate model of power consumption in embedded memory blocks. A software neural-network is used to create a regression tree by automatically splitting those variables that have a discontinuous effect on the power consumption. An application of the methodology to the modeling of a 0.35µm CMOS embedded SRAM is presented.

Power dissipation in digital circuits is strongly pattern dependent. Thus, to derive accurate simulation-based power estimates, a large amount of input vectors is usually required. This paper proposes a vector compaction technique aiming at providing accurate power figures in a shorter simulation time for complex sequential circuits characterized by some hundreds of inputs. From pair-wise spatio-temporal signal correlations, the proposed approach is based on bit clustering and temporal partitioning of the input stream aiming at preserving the statistical properties of the original stream and maintaining the typical switching behavior of the circuit. The effectiveness of the proposed approach has been demonstrated over a significant set of industrial case studies implemented in CMOS submicron technology. While achieving a 10x to 50x stream size reduction, the reported results show an average and maximum errors of 2.4% and 7.1% respectively, over the simulation-based power estimates derived from the original input stream.

In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models and it usuallyrequires less simulations for the cell characterization.Moreover it is compatible with the most advanced interconnectdelay models that have been recently proposed inthe literature.

A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.

This paper discusses manufacturabilty of state-of-the-art low power technologies.We report the results on two generations of bulk CMOS technologies, triple-well CMOS and Thin Film Silicon on Insulator (TFSOI) technologies.We present technology capabilities for several values of supply voltage and address the issue of performance scaling with the supply voltage reduction.Then we focus on the statistical characterization of these technologies and discuss both interchip and intrachip variations.Finally, we present the digital and analog designer perspectives on the low power IC operation.

The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to exploit all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.