Asynchronous CMOS circuits have the potential for very low power consumption, because they only dissipate when and where active. In addition they have favorable EMC properties, since they emit less energy, which in addition is evenly distributed over the spectrum. The Tangram framework supports the design of asynchronous circuits in a high-level programming language. Using this framework we have designed several chips, such as for instance for pagers and smart cards, which are clearly superior to synchronous designs.

We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40% larger in size than synchronous designs. For the total pager unit this means a 37% reduction in power dissipation for nearly no additional area. The decoded chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In an appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size.

A local area network (LAN) design based on a ring topology is presented which can support both packet-switched and circuit-switched traffic. The packet-switching service is reliable in that the LAN controllers deal with all protocol problems, i.e., medium arbitrations as well as flow and error control. The service can meet real-time constraints, since the performance is stable under high load conditions and the arbitration delays are bounded. Moreover, the processing speed of the LAN controller is independent of the transmission speed, and the speed requirements are such that they can be met by a microprocessor (no need for dedicated hardware to process the information on the fly). Before the design of PHILAN is presented, an analysis is given of the protocol problems that have to be dealt with when establishing a reliable packet-switching service on a LAN.>

Two designs of a fault-tolerant clocking system are described: a time-discrete design based on autonomous oscillators and a time-continuous design based on voltage-controlled oscillators. In both designs the system consists of a number of identical modules producing as many mutually synchronous binary clock signals. The system is fault-tolerant in that if at most f modules fail, the remaining modules continue to produce synchronous clock signals. The minimum configuration, i.e., the minimum number of modules that guarantees a fault-tolerant operation, is either 3f + 1 or 2f + 1, depending on both the design chosen (time-discrete or time-continuous) and the assumed fault model.

A construct is proposed for parallel programming, called soma (software machine). A soma is a sequential process that can communicate with other somas by exchanging messages via mailboxes. The soma construct is well suited for implementation on conventional as well as on distributed computer architectures, the main characteristic of the latter being the absence of a common store.

The DIMOND is a building block for communication networks in which throughput is more important than transmission delay. Its main attraction stems from the fact that it allows the routing of messages through a network to be completely distributed over the individual building blocks.