In this paper, we propose a battery-powered wild animal tracking device using a Pan-Tilt-Zoom (PTZ) camera and deep learning. The proposed tracking device detects wild animals using YOLOv5 and tracks the detected wild animals using DeepSort. In addition, the proposed tracking device realizes tracking for a wide range by controlling a PTZ camera according to the movement direction of the detected wild animals. In the experiment, we developed a prototype for the proposed tracking device and conducted the field test of the developed prototype. We confirmed and discussed cases where the developed prototype could and could not track wild animals. The energy consumption of the developed prototype during tracking was 526.03J at the daytime and 730.99J at the nighttime.

Understanding the degree of satisfaction for visitors has been a key factor in selecting attractive collections and designing appealing layouts in art galleries and museums. Although monitoring the actual spatiotemporal behaviors of visitors is essential for this purpose, introducing an expensive monitoring system would impose a heavy burden on the financial management and leads to unwanted restrictions on the layout design in the exhibition rooms. This paper presents an approach to visualizing the spatiotemporal changes in the maps of visitors' interest with a system of installed single-board computers such as Raspberry Pi devices. Employing single-board computers as IoT sensors facilitates monitoring systems to maximally covers the entire exhibition space while keeping the associated installation cost and power consumption sufficiently low. Our approach for this novel system organization begins by first detecting individuals from camera images using machine learning techniques and reconstructing their spatial positions from perspective views. Kernel density estimation was employed to represent the distribution of interest across the entire exhibition room as a continuous function by respecting the reconstructed positions of visitors. This allowed the use of heatmaps to visualize the changes in the map of interest reflecting the travel history of individual visitors and the accumulated distribution of interest over a specific period. Experimental results from eight months of measurement data demonstrate the capability of the proposed approach, including meaningful trends that reveal how the layout of collections attracted visitors to the exhibitions.

The bear attack to human beings is one of the fatal accidents, and it is becoming more critical to avoid such accidents because human 's encountering a bear happens every year, even in a city area. It is required to discover bears quickly and warn people to avoid bear accidents. To realize sensor nodes that detect bears automatically using image recognition technology, we aim to realize an accurate and computationally-efficient bear-presence detection. In this paper, we propose a bear-presence detection method combining region proposal of a low-resolution and image classification. In the experiments, we show that the proposed method achieves 4.9% higher recall and 2.3% higher F-score than image classification with-out region-proposal. Moreover, the proposed method achieved 0.6% higher recall and 18.5% higher F-score than YOLOv3, which is one of state-of-the-art object detection methods while the execution time was reduced to 72.4% for bear images and 55.5% for non-bear images.

One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently, LELECUT type TPL technology, where the third mask is used to cut the patterns, is discussed to alleviate native conflict and overlay problems in LELELE type TPL. In this paper, we formulate LELECUT mask assignment problem which maximizes the compliance to the lithography and apply a positive semidefinite relaxation. In our proposed method, the positive semidefinite relaxation is defined by extracting cut candidates from the layout, and a mask assignment is obtained from an optimum solution of the relaxation by randomized rounding technique.

Multi-domain clock skew scheduling is an effective technique to improve the performance of sequential circuits by using practical clock distribution network. Although the upper bound of performance of a circuit increases as the number of clock domains increases in multi-domain clock skew scheduling, the improvement of the performance becomes smaller while the cost of clock distribution network increases much. In this paper, a linear time algorithm that finds an optimum two-domain clock skew schedule is proposed. Experimental results on ISCAS89 benchmark circuits and artificial data show that optimum circuits are efficiently obtained by our method in short time.

In recent Printed Circuit Boards (PCB) routing and package routing, any-angle gridless routing is required since the density has increased and the specification becomes severe. In this paper, we propose a routing method which solves an any-angle gridless routing problem by formulating the problem by non-linear programming which is solved by quasi-Newton method. Our proposed method minimizes the total wire length or the total length error while satisfying constraints such as the separation for a route and an obstacle, the separation for two routes, and the angle of bend in a route. Experiments show that the proposed method is effective to obtain any-angle gridless routes in short computational time.

In this paper, we propose CAFE router which obtains routes of multiple nets with target wire lengths for single layer routing grid with obstacles. CAFE router extends the route of each net from a pin to the other pin greedily so that the wire length of the net approaches its target wire length. Experiments show that CAFE router obtains the routes of nets with small length error in short time.

In recent VLSI systems, signal propagation delays are requested to achieve the specifications with very high accuracy. In order to meet the specifications, the routing of a net often needs to be detoured in order to increase the routing delay. A routing method should utilize a routing area with obstacles as much as possible in order to realize the specifications of nets simultaneously. In this paper, a fast longer path algorithm that generates a path of a net in routing grid so that the length is increased as much as possible is proposed. In the proposed algorithm, an upper bound for the length in which the structure of a routing area is taken into account is used. Experiments show that our algorithm utilizes a routing area with obstacles efficiently.

The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast power estimation method for the clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed power estimation method, the proposed clock scheduling method finds clock schedules for benchmark circuits that greatly reduce the peak power in a few minutes.

Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. But if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a register relocation method that reduces the number of registers while keeping the target clock period. The proposed method reduces the number of registers in the practical time in experiments.

In our dynamically reconfigurable system model, computation resources are arranged in 2D-plane and each partial task is assigned to computation resources of rectangle-shape for a certain time period. The problem can be regarded as a rectangular box packing problem in 3D-space of 2D-plane and time axis. However, since partial tasks have order constraints, a packing should satisfy the given order constraints. We call this problem 3D-scheduling problem. Although there have been proposed various types of rectangular box packing representation, it is not examined until now which representation is fit to 3D-scheduling problem. In this paper, we investigate features of each 3D-packing representation, and show which representation is fit to 3D-scheduling problem theoretically and experimentally