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Igor Keller

dblp:67/1140 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › signal integrity
noise modeling
0.112008
Challenges in gate level modeling for delay and SI at 65nm and below · DAC 2008
Electronic design automation
signal integrity
0.112008
Challenges in gate level modeling for delay and SI at 65nm and below · DAC 2008
Electronic design automation
timing analysis
0.112008
Challenges in gate level modeling for delay and SI at 65nm and below · DAC 2008

Methods — techniques the papers use, named apart from their topics

standard cell modeling · 0.1
YearPublicationVenuePosition
2014 TAU 2014 contest on removing common path pessimism during timing analysis
abstract
To protect against modeling limitations in considering design and electrical complexities, as well as variability, early and late signal propagation times in static timing analysis are often made pessimistic by addition of extra guard bands. However, these forced early-late splits introduce excessive and undesired pessimism. To this end, common path pessimism removal (CPPR) eliminates guaranteed redundant pessimism during timing analysis. This session aims to highlight the importance of CPPR during timing analysis, as well as explore novel methods for fast CPPR from the top performers of the TAU 2014 timing contest.
Debjit Sinha, Igor Keller
ICCAD3
2014 TAU 2014 contest on removing common path pessimism during timing analysis
abstract
To margin against modeling limitations in considering design and electrical complexities (e.g., crosstalk coupling, voltage drops) as well as variability (e.g., manufacturing process, environmental), "early" and "late" signal propagation delays in static timing analysis are often made pessimistic by addition of extra guard bands. While these forced "early-late splits" provide desired margins, the splits applied across the entire design introduce excessive and undesired pessimism. To this end, "common path pessimism removal (CPPR)" eliminates the redundant pessimism during timing analysis.
Debjit Sinha, Igor Keller
ISPD3
2008 Challenges in gate level modeling for delay and SI at 65nm and below
abstract
In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.
Igor Keller, King Ho Tam, Vinod Kariat
DAC1
2004 A robust cell-level crosstalk delay change analysis
abstract
In This work we present a robust and efficient methodology for crosstalk-induced delay change analysis for ASIC design styles. The approach employs optimization methods to search for worst aggressor alignment, and it computes crosstalk induced delay change on each stage considering an impact on downstream logic. Computational efficiency is achieved using pre-characterized current models for drivers and compact macromodels for interconnect. The proposed methodology has been implemented in a commercial noise analysis tool. Experimental results obtained on industrial designs demonstrate high accuracy and reduced pessimism of the proposed methodology.
Igor Keller, Ken Tseng, Nishath K. Verghese
ICCAD1