We propose a novel computer architectural concept of instruction overloading to support block ciphers. Instead of adding new instructions, we extend only the execution of some existing instructions. The proposed method allows a central processing unit core to execute different operations for the same instructions, depending on the address of the data, similar to operator overloading in object-oriented languages. We first present an extension for the AES algorithm, then we demonstrate its enhanced applicability with two further extensions supporting multiple block ciphers and hardware masking. The first extension for AES is also applicable to add/AND-rotate-XOR-based block ciphers such as SIMON. The AES and SIMON encryption speed, on this extended core, is at least doubled and is significantly less affected by memory latency. In addition, the AES encryption code requires only 18% of the memory of the previous software implementation. The second extension can further support various block ciphers defined over GF(28), and the SM4 encryption speed is increased by at least 182%. The third extension provides correlation power analysis (CPA) resistance with a 66.6% area overhead but almost no speed overhead, whereas a typical software anti-CPA AES implementation requires at least hundreds of times the execution time.

Montgomery reduction is a well-known optimization technique for modular reduction over prime fields. However, it has rarely been used for national institute of standards and technology (NIST) prime fields, because the special structure of NIST primes enables fast reduction that requires fewer computations than Montgomery reduction. In this study, we rediscover the Montgomery reduction for NIST primes and propose a new modular reduction method by applying partial modular reduction to Montgomery reduction. Using this new modular reduction method and other optimization techniques, such as pipelining and parallel processing, we propose an efficient elliptic curve cryptography (ECC) coprocessor over NIST prime fields. The implementation results indicate that the proposed coprocessor can perform one elliptic curve point multiplication in 0.055 ms with only 194.7 k gate counts. This is a considerably higher speed per area compared to previous research.

A Personal Identification Number (PIN) is a multiple-digit sequence widely used for user authentication . It is desirable for a PIN-entry method to be secure against two main security threats, random guessing attacks and recording attacks. Although there have been many proposals for challenge-response-based PIN-entry methods, it is well known that the only way to prevent both attacks is to physically prevent attackers from observing the challenge-response pairs, which motivates the development of PIN-entry methods that use secure secondary channels such as audio signals . To provide a guideline for designing an audio-based PIN-entry method, we propose a simple framework to transform a non-audio-based method into an audio-based one. We also present a new PIN-entry method that improves the performance of this simple transformation. Most audio-based methods in the literature are unimodal methods, that is, they transmit almost all required information through an audio channel because it was believed that this approach maximized the user's performance. In this paper, however, we show that a carefully designed bimodal system may be more usable than a unimodal one. We present a new PIN-entry method whose audio channel only transmits the minimal required data while most of the challenge information is transmitted through the efficient visual channel. Our user study shows that the PIN-entry time of the proposed method is shorter than those of the previous audio-based methods, while its error rate is kept as low as that of the previous methods.

This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments. To overcome this issue, we previously proposed the differential amplifier PUF (DA-PUF) which improves the reliability by amplifying the small mismatches of the transistors and rejecting the power supply noise through differential operation. In this paper, we first report the experimental results with the fabricated chips in a 0.35 µm CMOS process. The DA-PUF shows 51.30% uniformity, 50.05% uniqueness, and 0.43% maximum BER. For 0% BER, we proposed the physical-based VIA-PUF which is based on the probability of physical connection between the electrical layers. From the experimental results with the fabricated chips in a 0.18 µm CMOS process, we found the VIA-PUF has 51.12% uniformity and 49.64% uniqueness, and 0% BER throughout 1,000-time repeated measurements. Especially, we have no bit change after the stress test at 25 and 125 °C for 96 hours.

A TPM (Trusted Platform Module) is a hardware-based secure device that is very strong against software-based attacks; however, the keys inside a TPM can be extracted by invasive physical attacks such as memory attacks and bus probing attacks. To protect the keys from these threats, we propose a new TPM architecture based on a Physical Unclonable Function.