Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Shigeki Shibayama

dblp:67/3272 · DBLP profile ↗
← Back
6ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-authorSoftware engineering, systems software and programming languages · 2Databases, data management, data science and information retrieval · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Memory systems · 48% Hardware accelerators and domain-specific architectures · 23% Parallel and multicore computing · 20%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%
Databases, data mining, and information retrieval
3 papers
Query processing and optimization · 38% Data models and query languages · 22% Data integration and cleaning · 22%

Topics — the 9 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Operating systems › resource management › process management › CPU scheduling
thread scheduling
0.011997
Distributed-Thread Scheduling Methods for Reducing Page-Thrashing · HPDC 1997
Memory systems › shared memory
distributed shared memory
0.011997
Distributed-Thread Scheduling Methods for Reducing Page-Thrashing · HPDC 1997
Parallel and multicore computing › parallel programming runtimes › thread management
thread migration
0.011997
Distributed-Thread Scheduling Methods for Reducing Page-Thrashing · HPDC 1997
Query processing and optimization
join processing
0.011988
Parallel Control Technique and Performance of an MPPM Knowledge-Base Machine · ICDE 1988
Hardware accelerators and domain-specific architectures › database accelerator
database machine
0.011985
A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware · ISCA 1985
Integrated circuit design › digital circuit design › VLSI architecture
sorting hardware
0.011985
A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware · ISCA 1985
Database system architecture and tuning › database machine
relational database machine
0.011983
A Relational Data Base Machine: First Step to Knowledge Base Machine · ISCA 1983
Parallel and multicore computing
parallel query processing
0.011988
Parallel Control Technique and Performance of an MPPM Knowledge-Base Machine · ICDE 1988
Parallel and multicore computing › parallel computing
fifth generation computer system
0.011983
A Relational Data Base Machine: First Step to Knowledge Base Machine · ISCA 1983

Methods — techniques the papers use, named apart from their topics

user-level threads · 0.0analytical modeling · 0.0unification engine · 0.0parallel control · 0.0multiport page-memory · 0.0two-way merge sort · 0.0least fixed point · 0.0hardware pipeline · 0.0deferred evaluation · 0.0
YearPublicationVenuePosition
1997 Distributed-Thread Scheduling Methods for Reducing Page-Thrashing
abstract
Although distributed threads on distributed shared memory (DSM) provide an easy programming model for distributed computer systems, it is not easy to build a high performance system with them, because a software DSM system is prone to page-thrashing. One way to reduce page-thrashing is to utilize thread migration, which leads to changes in page access patterns on DSM. In this paper, we propose thread scheduling methods based upon page access information and discuss an analytical model for evaluating this information. Then, we describe our implementation of distributed threads, PARSEC (Parallel software environment for workstation cluster). Using user-level threads, PARSEC implements thread migration and thread scheduling based upon the page access information. We also measure the performance of some applications with these thread scheduling methods. These measurements indicate that the thread scheduling methods greatly reduce page-thrashing and improve total system performance.
Yoshiaki Sudo, Shigeo Suzuki, Shigeki Shibayama
HPDC3
1996 An Optical Bus Computer Cluster with a deferred cache coherence protocol
abstract
In this paper, we first propose a class of workstation cluster which utilizes optical wavelength-division multiplexing (WDM) technology to connect nodes (work-stations) of the cluster. The Optical Bus Computer Cluster (OBCC) falls in the class of cache coherent non-uniform memory access (CC-NUMA) multiprocessors. The basic topology of the cluster is star-shaped with an optical star-coupler in the center to enable one-hop simultaneous broadcasting of information packets from one node to all other cluster nodes. WDM technology not only multiplies by N times the network bandwidth using a single optical fiber, where N is the degree of wavelength multiplexing, but also provides independent communication paths between pairs of cluster nodes by properly assigning wavelengths to inter-node communication. Then we identify the cache subsystem requirements for the OBCC and propose or deferred cache coherence protocol suitable for the OBCC. The basic coherence maintenance scheme is to lazy-evaluate the cache coherence transactions among cluster nodes, utilizing the weak consistency memory model. By deferring the transactions, it is possible to combine multiple transaction issues into one transaction by accumulating modified status bits in the enhanced cache status fields. Since not only the remote memory access but also coherence transaction are costly operations in CC-NUMA systems, the deferred invocation of coherence transactions is particularly useful in CC-NUMA systems such as OBCC. We then give a performance evaluation by simulation that the coherence protocol effectively reduces coherence transactions, particularly in situations where false sharing of longer cache lines becomes noticeable.
Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura
ICPADS1
1988 Parallel Control Technique and Performance of an MPPM Knowledge-Base Machine
abstract
A description is given of parallel control techniques and performance evaluations by simulation for the knowledge-base machine (KBM) using the multiport page-memory (MPPM) and the unification engine (UE). Relational knowledge base retrieval requires repeated application of the unification-join (U-join) operations on term relations. It also requires each U-join to be dynamically scheduled, observing the result of the previously executed U-join. Control techniques to execute the query process of the relational knowledge base effectively in the KBM using the MPPM and the UE have been investigated. For parallel execution of coarse-grain operations, each operation is decomposed to concurrently executable fine-grain operations by partitioning input data sets. A number of features that depend on processor-allocation strategies have been identified. In particular, it was found that query processing resulting in repetitions of the retrieval operation, by a certain control strategy, increases the amount of the total data transfer to the highly parallel UEs and lowers processing efficiency.>
Hidetoshi Monoi, Yukihiro Morita, Hidenori Itoh, Hiroshi Sakai, Shigeki Shibayama
ICDE5
1985 A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware
abstract
A relational database machine Delta [2] has been developed at the Institute for New Generation Computer Technology (IOOT).The main component of Delta is an RDBE (relational database engine)[3] which performs relational database operations, such as projection and join.The RDBE consists of a sorting process hardware module called the sorter, a merging process hardware module called the merger, other special hardware modules called the IN module, a data input adapter, a data output adapter, and a CPU controlling these hardware modules.A special sorting cell was developed and implemented on LSI.The sorting process is based on a two-way merge-sort algorithm [l].~ne merging process is based on a hardware pipeline algorithm.In this paper, we describe the design considerations of the RDBE and these algorithms.Then, we describe the detailed design, implementation, and a performance evaluation of the RDBE.
Shigeo Kamiya, Kazuhide Iwata, Hiroshi Sakai, Susumu Matsuda, Shigeki Shibayama, Kunio Murakami
ISCA5
1984 An Enhanced Inference Mechanism for Generating Relational Algebra Queries
abstract
A system for interfacing Prolog programs with relational algebra is presented. The system produces relational algebra queries using a deferred evaluation approach. Least fixed point (LFP) queries are automatically managed. An optimization method for removing redundant relations is also presented.
Haruo Yokota, Susumu Kunifuji, Takeo Kakuta, Nobuyoshi Miyazaki, Shigeki Shibayama, Kunio Murakami
PODS5
1983 A Relational Data Base Machine: First Step to Knowledge Base Machine
abstract
The Japan's Fifth Generation Computer System project is divided into three stages. In the first three-year stage, a working relational data base machine is developed for a software development support system to be used in the second stage and also for an experimental system which provides a research tool for the knowledge base machine.
Kunio Murakami, Takeo Kakuta, Nobuyoshi Miyazaki, Shigeki Shibayama, Haruo Yokota
ISCA4