Scale-Invariant Feature Transform (SIFT) [1] has lately attracted attention in computer vision as a robust feature point detection algorithm which is invariant for scale, rotation and illumination change. However, its computational complexity is too high to apply on practical real-time applications. The iterated Gaussian blurred operations on images lead to long computational latency and high memory requirement. In addition, the gradient histogram based descriptor needs lots of calculation and costs about 60% of total calculation time on generating the descriptor. We propose a binary-based descriptor that uses the intensity difference between neighboring pixels. The binary descriptor has the advantage of lower computational complexity and memory usage. For the use of the classifying the object, the binary descriptor also have the acceptable accuracy compared with the traditional histogram based descriptor. The proposed binary descriptor has 7.07x speed up than the original SIFT descriptor. In addition, it has 4.73x speed up compared with original SIFT algorithm [1]. The hardware implementation of the SIFT algorithm with the proposed binary descriptor applies parallel computing on the stage of feature location to accelerate the computing time on detecting feature points. The final implementation uses about 493-K gate count with 90-nm CMOS technology, and offers 7600 feature points/frame for 1080p images at 30 frames/s at the clock rate of 100 MHz.

Traditionally, an adaptive boosting (AdaBoost) algorithm is used for object recognition because of its prevalent usage and well-trained results. However, because the computation of AdaBoost is extremely time-consuming, it is difficult to guarantee that the computations reflect the latest information in real time. To speed-up the operation, the original AdaBoost algorithm was accelerated with a graphics processing unit (GPU). In this study, Compute Unified Device Architecture (CUDA) was used to accelerate two parts of the AdaBoost algorithm, including feature extraction and training, by applying various strategies to system components such as how the data is put in the memory, amount of CUDA streams, trunk size, and block size. In Feature Extraction of the car datasets, the most time-consuming step feature-value computation is 47.18 times faster than the CPU version. For AdaBoost Training, the total execution is accelerated by 34.23 times.

As the CMOS technology develops, the number of buffers required in a network-on-chip increases with flit width. This increase of buffers provides more power and area overhead to a network router. This paper proposes a hybrid packet-switched and circuit-switched network in which the total buffer requirement depends on only the width of the short message and buffer depth, and does not increase with the network width. The performance is maintained through a low latency circuit-switch by using a simple reverse path reservation method. The simulation results indicated that a considerable amount of power and area can be saved by the buffer reduction, whereas performance is maintained.

A load-balanced Birkhoff-von Neumann (LB-BvN) 4 × 4 switch fabric IC is proposed for feedback-based switch systems. This is fabricated in 0.13- μm CMOS technology and the chip area is 1.380 × 1.080 mm2. The overall data rate of the LB-BvN 4 × 4 switch fabric IC is up to 32 Gb/s (8 Gb/s/channel) with only 0.8 ns propagation delay. The LB-BvN switch is highly recommended for constructing the next-generation terabit switch. In a feedback-based switch system, the long propagation delay of the switch module reduces the system throughput significantly. In this paper, we present a scalable LB-BvN 4 × 4 switch fabric IC directly in the high-speed domain. By observing the deterministic switching pattern of the N×N LB-BvN switch, we present a low-complexity pattern generator that reduces the PG complexity from O(N3) to O(1). This technique reduces the propagation delay of the switch module from 30 to 0.8 ns, and also provides 80% area saving and 85% power saving compared to serializer-deserializer interfaces. The proposed LB-BvN 4 × 4 switch fabric IC is suitable for feedback-based switch systems to solve the throughput degradation problem.

This paper proposes Multiplexer-Flip-Flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose Multiplexer-Latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis shows that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to the traditional pipeline topology. To verify the function of the proposed design, a chips is implemented with the proposed 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the proposed serializer with MUX-FFs are bit-error-free (with BER-12), operating at up to 12 Gbit/s.

In this paper, a low propagation delay, low power, and area-efficient 4×4 load-balanced switch circuit for feedback-based system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based N×N switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4×4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).

Hybrid networks, which combine the flexibility of packet-switched network and the low-latency of circuit-switched network, provide decent performance. However, users are obligated to maintain the configuration of temporary circuit-switched connection. In this paper, we propose Dynamic Bypass Circuit, a novel architecture which reconfigures a mesh network according to the traffic trends of applications at run-time. Additionally, in order to create more obvious trends for Dynamic Bypass Circuit, we propose north-last-weave routing algorithm. It guides packets toward different directions according to the positions of their source nodes. Simulation results show that dynamic reconfigurable NoC which adopts Dynamic Bypass Circuit outperforms traditional packet-switched network. The latency improvement is 18.08% under Transpose traffic and on average 13.05% under three different traffic patterns.

This work presents a new scheme of reliability mechanism in storage systems. The new scheme defines reliability and protects data in the scope of file, which is very different from traditional strategies, which protect data in the scopes of storage block or the whole device. The scheme provides the possibility to store highly reliable files and normal ones under the same file system, increasing flexibilities and decreasing costs of storage systems. To implement this scheme, Linux virtual file system (VFS) layer has been modified to perform reliability related operations during I/O calling paths and provide new interfaces for file systems to define their own reliability methods. A modified Ext2 file system with different levels of reliability has also been built as an example design of the new scheme. Depending on reliability levels, files in the example design are protected by parity check and Reed-Solomon Code of different code rates, which incur different overheads.

In this paper, a low propagation delay, low power, and area-efficient 4×4 load-balanced switch circuit for feedback-based system is presented. In this periodic and deterministic switch, only two DFFs are used to implement a pattern generator which is a O(N3) hardware complexity in traditional matching algorithm based N×N switch. For packet reordering, a feedback path is established in series of symmetric patterns. As comparing with commercial switch systems, we implement a 4×4 switch IC directly in high speed domain without the use of SERDES interfaces to achieve low propagation delay and high scalability. In CML output buffer, PMOS active load and active back-end termination are introduced. A stacked current source and symmetric topology in CML-DFF are adopted. From our results, this work efficiently deducted 28ns propagation delay, 80% area and 80% power introduced by the SERDES interface. The throughput rate is up to 32Gbps (8Gbps/Ch).

In this paper, a novel multiplexer-flip-flop (MUX-FF) topology using the current mode logic (CML) is presented. A CML multiplexer-latch (MUX-latch) is proposed by combining a multiplexer and the loopback storage part of a latch into a single module so that the buffer part of a latch can be removed. A MUX-FF is implemented by cascading two stages of MUX-latches. The output of a MUX-FF is edge-triggered, so it is insensitive to input noise. All the paths from inputs to the output are symmetric. Power and area can be reduced due to the removal of DFFs. Simulation results show that a MUX-FF can achieve a similar frequency as a conventional tree-type MUX by saving 56% of area and 72% of power consumption.

Network-on-Chip (NoC) is a key component in the design of many cores on a chip. This paper presents a new system level NoC simulation framework, called “Network-On-Chip-centric System Exploration Platform” (NOCSEP). It divides NoC design space into blocks and models them using abstracted layers. Together with task-graph software modeling and simplified middle-layer modeling, it can estimate the performance of an on-chip interconnect rapidly and is therefore very suitable for quickly exploring design alternatives.

In this paper, a cycle stealing buffer and a physical channel management scheme are proposed for the design of on-chip networks. The cycle stealing buffer can reduce the number of cycles in reading and writing a network buffer. The physical channel management scheme can efficiently multiplex and arbitrate the physical channel among many virtual channels. These two methods can be adopted in wormhole based networks to improve both latency and throughput. In this paper, by use of simulation, we study the feasibility and benefits of these two methods using wormhole based ring and torus networks.

In this paper, we present a 7 Gbps/Ch quad SerDes integrated with a 4times4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1 ps. The total area is 3 mm times 2.48 mm, including the switch fabric, the quad SerDes interface, and a LC-PLL. In our results, each input/output port of the 4x4 switch fabric can achieve 7 Gbps data rate, and the overall throughout is 28 Gbps.

For the first time, a scalable load balanced Birkhoff-von Neumann TDM switch IC with SERDES interface circuits for high speed networking applications was implemented. AnyN×NBirkhoff-von Neumann TDM switch could be constructed recursively from the designed TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8×8 TDM switch core with 8B10B codecs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All the implementations were based on the 0.18 μm CMOS technology. Test results showed a 20 Gbps switching capacity for the 8×8 TDM switch IC.

This paper studies the memory system behavior of Java programs by analyzing memory reference traces of several SPECjvm98 applications running with a Just-In-Time (JIT) compiler. Trace information is collected by an exception-based tracing tool called JTRACE, without any instrumentation to the Java programs or the JIT compiler.

Presented are the resr.dts of a study conducted to evaluate the performance of parailel 1/0 on a massiveiy parallel processor (MPP).The network traversal and total processing times are calculated for [/0 reads and wriles whiie vaying the 1/0 and non-I/O request rates and the request size.A Iso studied is the performance impact of I/O and non-I/O traffic on each other.The resuits show that the system is scalable for I/O loads considered; however, the scalability is limited by 1/0 node saturation or considerable network contention.

Stack simulation is a powerful cache analysis approach to generate the number of misses and write backs for various cache configurations in a single run. Unfortunately, none of the previous work on stack simulation has efficient stack algorithm for virtual address caches with real tags (VIR-type caches). In this paper, we devise an efficient stack simulation algorithm for analyzing VIR-type caches. Using markers with a valid range for synonym lines, our algorithm is able to keep track of stack distances for different cache configurations. In addition to cache miss ratios and write back ratios, our approach generates pseudonym frequency for all cache configurations under investigation.>

We propose efficient stack simulation algorithms for shared memory multiprocessor (MP) caches. A stack simulation algorithm for write-updated MP caches is first presented. It produces the number of write-updates as well as misses for all cache configurations in a single run. We then devise a new stack simulation algorithm for writeinvalidate MP caches. Our algorithm takes into account cross-invalidation among processors, and generates the number of invalidations as well as misses for all cache configurations in a single run. A cache simulator based on our algorithms for MP caches is developed and the results on sample traces are reported. Our results show that effi cient stack simulation is a powerful technique for multi processor cache analysis.

Parallel accesses to the table lookaside buffer (TLB) and cache array are crucial for high-performance computer systems, and the choice of cache types is one of the most important factors affecting cache performance. The authors classify caches according to both index and tag. Since both index and tag could be either virtual (V) or real (R), their classification results in four combinations or cache types. The real address caches with virtual tags for high-performance computer systems in this study are prediction-based, since index bins are generated from a small array and predictions could be false. As a result, they also discuss and evaluate real address MRU caches with real tags, and propose virtually indexed MRU caches with real tags. Each of the four cache types and MRU caches are discussed and evaluated using trace-driven simulation. The results show that a virtually indexed MRU cache with real tags is a good choice for high-performance computer systems.>

Efficient stack simulation has been successfully applied in physically indexed caches with physical or real tags to generate the number of misses and write backs for various cache configurations in a single run. The authors devise a stack simulation algorithm for virtually indexed caches with real tags. Using markers with a valid range for synonym lines, the algorithm is able to keep track of stack distances for various cache configurations. In addition to cache miss ratios and number of write backs, the algorithm reports pseudonym frequency for all cache configurations under investigation. A one-pass cache simulator based on the algorithm is developed, and its results on sample traces are reported.>

Performance of the wraparound network through trace-driven simulation is examined. This network has a processor attached to each node, but the links in the network are unidirectional, and the two ends of the network are joined together. Traces of three representative parallel engineering/scientific programs are used as input to the simulator, and the performance of this network is compared to that of an omega network under the same inputs. The wraparound network and the omega network are found to perform similarly, while the size and cost of the wraparound network are smaller than those of the omega.>

A novel VLSI message switch design for application in highly parallel architectures is presented. The prominent features of this design are message combining, a shared central queue structure with a dynamic boundary and nonpreemptive priority, and a look-ahead protocol between switch nodes in adjacent stages. These features alleviate memory contention and increase the effective network bandwidth.>