Power/signal delivering network for 2D systems comprising a package and an Integrated Circuit (IC) are design tasks that can be concurrently handled today. Design iterations can be locally carried out in each subsystem part without the need to modify the other one's decisions. This is unfortunately not the case in 2.5D/3D stacked systems. Finer system integration technology, either via Through Silicon Stack (TSS) and/or Through Silicon Interposer (TSI), involves tighter evaluation of the coupling effects in the system-wide PDN impedance and Signal Integrity (SI) characteristics. If these interactions are not properly accounted early in the design cycle, undesired design loop iterations, affecting design productivity is possible. Therefore, new tools and flows incorporating abstracted physical information of the PDN and signal interconnect stack architecture are needed for early design exploration. This paper elaborates on the problems, tool flows and methods necessary to address these challenges for 2.5D/3D stacked systems.

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.

The continuation of Moore's law by conventional CMOS scaling is becoming challenging. 3D Packaging with 3D through silicon vias (TSV) interconnects is showing promise for extending scaling using mature silicon technology, providing another path towards the "More than Moore". Two years ago, the big unceasing question was "Why 3D?" Today, as we move forward with the concrete implementation of the technology, the questions are now "When 3D?" and "How 3D?" There are quite a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it. However, for many the lingering questions remain "Are we there yet?" "Is it now or the future?"

Given the exponential increase of fabrication costs, the global recession and credit crunch, one may ask if Moore's Law is financially viable beyond 22nm node. Can we justify the return-of-investment (ROI) for continuous scaling beyond 22nm? Shall we consider other alternatives for integration, such as silicon-in-a-package (SiP) or 3D integrations?

As CMOS technology is scaled beyond 45nm, SOC/SiP design for wireless chips is increasingly constrained by fundamental technology limits, resulting in challenges including parametric variability, leakage, active power, signal integrity, and diminished performance improvement. New materials and innovative device structures are needed to extend CMOS scaling and integrate disruptive More than Moore functionality, but these can have adverse impact on manufacturing cost and risk. Hence, tradeoff analysis spanning process, device, circuit, memory, package, architecture, software, and business disciplines is required during the advanced technology development cycle to explore and co-optimize technology and design choices. Such methodology, in conjunction with judicious use of test chips, also provides for a bridge from innovative technology solutions to mainstream product adoption.Several approaches are currently in use for ad-hoc exploration of advanced technology and design - typically based on spreadsheet analysis, guru consultation, and/or full trial designs. With the exploding complexity of the optimization space, subject matter knowledge and expert experience needs to be complemented with a structured methodology and tools. A Holistic methodology is proposed for addressing technology and design tradeoffs early in the development cycle to allow co-optimization all the way up to the system architecture level. A virtual design flow that allows rapid estimation of performance, power and cost attributes of a potential product, as a function of a given set of process or design assumptions is described as shown in Figure 1. Key target features of such a virtual flow and a summary of the attributes of several candidate point tools is presented. Requirements for the tools and methodologies to be used for Pathfinding across the span of disciplines are outlined. In order to enable system cost and performance/power analyses, the requirements for predictive models that describe variability, leakage, devices, interconnect, and DFM attributes are identified.Examples of Pathfinding application for co-optimization of memory technology and architecture, reduced parametric variability using restricted physical design rules, and exploration of 3D chip stacking are presented to highlight the requirements and gaps in the existing EDA tool solutions. The vision is for a design exploration platform that outputs performance, active and standby power, and cost estimates in reasonable response time, and with physical and variation awareness at the architectural level.

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability.As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, Interconnect, Leff, Gate Width) and their impact on design tools and methodologies.What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability?Will conservative design to accommodate variability halt the progress of Moore's Law?Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?.

A fabless company perspective is presented on the roles of the foundries, design entities and EDA providers in the DFM arena, and the requirements for measurement of the economic benefits of DFM.