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Kenichi Hayashi

dblp:67/6826 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2015
0000-0002-3975-3005ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-authorArtificial intelligence and machine learning · 1Security and privacy · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 36% Parallel and multicore computing · 36% Performance modeling and evaluation · 22%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › multiprocessor system
distributed memory parallel computers
0.011994
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Processor architecture and microarchitecture
instruction set architecture
0.011994
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Parallel and multicore computing › parallel architecture
message-passing architecture
0.011993
Improving AP1000 Parallel Computer Performance with Message Communication · ISCA 1993
Performance modeling and evaluation › parallel system performance
message-passing performance
0.011993
Improving AP1000 Parallel Computer Performance with Message Communication · ISCA 1993
Processor architecture and microarchitecture
multiprocessor architecture
0.011993
Improving AP1000 Parallel Computer Performance with Message Communication · ISCA 1993
Interconnection networks and networks-on-chip › interprocessor communication
message-passing network
0.011994
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Performance modeling and evaluation › simulation › discrete-event simulation
trace-driven simulation
0.011993
Improving AP1000 Parallel Computer Performance with Message Communication · ISCA 1993

Methods — techniques the papers use, named apart from their topics

simulation · 0.0message-level simulation · 0.0
YearPublicationVenuePosition
2015 Clustering of multivariate binary data with dimension reduction via L1-regularized likelihood maximization
Michio Yamamoto, Kenichi Hayashi
Pattern Recognit.2
1997 Proposal of user identification scheme using mouse
Kenichi Hayashi, Eiji Okamoto, Masahiro Mambo
ICICS1
1994 AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler
abstract
The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.
Kenichi Hayashi, Tsunehisa Doi, Takeshi Horie, Yoichi Koyanagi, Osamu Shiraki, Nobutaka Imamura, Toshiyuki Shimizu, Hiroaki Ishihata, Tatsuya Shindo
ASPLOS1
1993 Improving AP1000 Parallel Computer Performance with Message Communication
abstract
The performance of message-passing applications depends on cpu speed, communication throughput and latency, and message handling overhead. In this paper we investigate the effect of varying these parameters and applying techniques to reduce message handling overhead on the execution efficiency of ten different applications. Using a message level simulator set up for the architecture of the AP1000, we showed that improving communication performance, especially message handling, improves total performance. If a cpu that is 32 times faster is provided, the total performance increases by less than ten times unless message handling overhead is reduced. Overlapping computation with message reception improves performance significantly. We also discuss how to improve the AP1000 architecture.
Takeshi Horie, Kenichi Hayashi, Toshiyuki Shimizu, Hiroaki Ishihata
ISCA2