Warpage is a major concern in fan-out wafer-level packaging (FOWLP) due to the complex thermal processing steps involved in manufacturing. These steps include curing, electroplating, and deposition, which induce residual stresses through differential thermal expansion and contraction of materials. This effect is further amplified by mismatches in the coefficients of thermal expansion (CTE) between different materials. In particular, high-density interconnects in the back-end of line (BEOL), redistribution layers (RDLs), and through-mold vias (TMVs) are susceptible to warpage-induced stress, strain, and deformation. This work conducts structural simulations to analyze warpage in the BEOL stack induced by FOWLP. Our results indicate that the impact of warpage is non-uniform across the entire BEOL geometry of a die, hence it impacts different metal layers differently, and different coordinates within one metal layer differently. We leverage this warpage analysis to calculate parasitics and evaluate the resulting changes in path delays.

Increasing microprocessor performance has historically been accompanied by increasing power and increasing on-chip power density, both of which present a cooling challenge. In this paper, the historical evolution of power is traced and the impact of power and power density on thermal solution designs is summarized. Industrial and academic researchers have correspondingly increased their focus on elucidating the problem and developing innovative solutions in devices, circuits, architectures, packaging and system level heatsinking. Examples of some of the current packaging and system thermal solutions are provided to illustrate the strategies used in their design. This is followed by a brief discussion of some of the future trends in demand and solution strategies that are being developed by academic and industrial researchers to meet these demands. Potential opportunities and limitations with these strategies are reviewed.