No abstract available.

The Planar Package Planner is a design aid aimed at helping to form a package layout plan, given only the information available during project initiation to digital system logic and package designers. A hierarchical approach is adopted, and a clustering program makes possible use of the layout scheme for bottom-up as well as top-down design. The layout plan for an experimental microprocessor is worked out as an example of the method.

The problems of designing and manufacturing systems made from integrated circuits have been changing rapidly as semiconductor technology has made greater circuit densities possible. Because of this rapid rate of change and the short time available for system design, it is essential to have reasonably accurate preliminary estimates of logic circuit counts, package sizes, and costs, as well as of design schedules. By preliminary, we mean prior to availability of circuit level system logic designs and/or prior to availability of partitioning, placement, and wiring aids to layout in a particular technology. The problem is complicated by the difference in difficulty between the predictability of wiring demand on packages with regular arrays of logic carriers and packages containing variably sized and shaped groups of logic circuits. Methods have been developed for preliminary estimation of wiring capacity in both these situations, and both methods and results will be discussed.