This paper studies the invariance of a given punctured convolutional code to an affine class of symbol transformations known to commonly occur in digital transceiver systems. A set of conditions to test the invariance of a code to these transformations has been derived, followed by two proposed methods to compensate for an invariant transformation. The viability of these methods has been examined by doing an invariant factor decomposition on the equivalent code generator matrix (obtained from the original code generator matrix and the given transform). The knowledge of the transformation and the nature of its occurrence greatly determines which method of compensation could be used. This study has much use in not only enabling a code designer to evaluate the invariance of an affine transformation to a given code, but also on the other hand to make the appropriate choice of code generators, puncturing schemes, and bit-to-constellation symbol mapping; so as to allow a channel coding scheme to be either sensitive or invariant to a given transformation, depending upon design objectives.

A seven-chip set which performs the functions associated with video and image compression algorithms, and CCITT H.261 in particular, has been designed, fabricated, and is fully functional. The major functions performed by the devices include motion estimation, DCT and IDCT, forward and inverse quantization, Huffman coding and decoding, BCH error correction, and loop filtering. The chips that perform the predictive and transform coding section of the algorithm operate with pixel rates up to 40 MHz. Array-based technologies of 1.5 and 1.0 mu m CMOS were used extensively to achieve a 28 man-month design time. Each die is less than 10 mm on a side.>

The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar number of additions) per second. The chip is reconfigurable for one- and two-dimensional filtering, the total device count is 240000 transistors, and the die size is 1.4 cm*1.4 cm. Tap design, data-flow organization, and clock distribution are discussed.>