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Daron Vroon 0001

dblp:68/6762 · DBLP profile ↗
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14ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 8Theory of computation · 7Artificial intelligence and machine learning · 4Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
3 papers
Program verification · 58% Requirements engineering and software design · 22% Program analysis · 19%
Theoretical computer science
2 papers
Automated reasoning and model checking · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Program verification
termination analysis
0.122006
Integrating static analysis and general-purpose theorem proving for termination analysis · ICSE 2006
Termination Analysis with Calling Context Graphs · CAV 2006
Requirements engineering and software design
software architecture
0.112007
Automating component-based system assembly · ISSTA 2007
Automated reasoning and model checking
model checking
0.112007
BAT: The Bit-Level Analysis Tool · CAV 2007
Automated reasoning and model checking
satisfiability
0.112007
Automating component-based system assembly · ISSTA 2007
Program analysis
static analysis
0.112006
Integrating static analysis and general-purpose theorem proving for termination analysis · ICSE 2006
Program verification
theorem proving
0.112006
Integrating static analysis and general-purpose theorem proving for termination analysis · ICSE 2006
Electronic design automation › hardware verification and test
hardware verification
0.012007
BAT: The Bit-Level Analysis Tool · CAV 2007

Methods — techniques the papers use, named apart from their topics

constraint solving · 0.1boolean satisfiability · 0.1bit-level analysis · 0.1SAT solving · 0.1theorem proving · 0.1calling context graphs · 0.1
YearPublicationVenuePosition
2011 The ACL2 Sedan Theorem Proving System
Harsh Raju Chamarthi, Peter C. Dillinger, Panagiotis Manolios, Daron Vroon 0001
TACAS4
2010 Interactive Termination Proofs Using Termination Cores
Panagiotis Manolios, Daron Vroon 0001
ITP2
2009 Faster SAT solving with better CNF generation
abstract
Boolean satisfiability (SAT) solving has become an enabling technology with wide-ranging applications in numerous disciplines. These applications tend to be most naturally encoded using arbitrary Boolean expressions, but to use modern SAT solvers, one has to generate expressions in conjunctive normal form (CNF). This process can significantly affect SAT solving times. In this paper, we introduce a new linear-time CNF generation algorithm. We have implemented our algorithm and have conducted extensive experiments, which show that our algorithm leads to faster SAT solving times and smaller CNF than existing approaches.
Benjamin Chambers, Panagiotis Manolios, Daron Vroon 0001
DATE3
2008 Efficient execution in an automated reasoning environment
abstract
Abstract We describe a method that permits the user of a mechanized mathematical logic to write elegant logical definitions while allowing sound and efficient execution. In particular, the features supporting this method allow the user to install, in a logically sound way, alternative executable counterparts for logically defined functions. These alternatives are often much more efficient than the logically equivalent terms they replace. These features have been implemented in the ACL2 theorem prover, and we discuss several applications of the features in ACL2.
David A. Greve, Matt Kaufmann, Panagiotis Manolios, J Strother Moore, Sandip Ray, José-Luis Ruiz-Reina, Robert W. Sumners, Daron Vroon 0001, Matthew Wilding
J. Funct. Program.8
2007 BAT: The Bit-Level Analysis Tool
Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001
CAV3
2007 Automating component-based system assembly
abstract
One of the major challenges in the development of large component-based software systems is the system assembly problem: from a sea of available components, which should be selected and how should they be connected, integrated, and assembled so that the overall system requirements are satisfied? We present a powerful framework for automatically solving the system assembly problem directly from system requirements. Our framework includes an expressive language for declaratively describing system-level requirements, including component interfaces and dependencies, resource requirements, safety properties, objective functions, and various types of constraints. We show how to automatically solve system assembly problems using verification technology that takes advantage of current advances in Boolean satisfiability methods. We have implemented our techniques in the CoBaSA tool (Component-Based System Assembly), and we have successfully applied it to several large-scale industrial examples.
Panagiotis Manolios, Daron Vroon 0001, Gayatri Subramanian
ISSTA2
2007 Efficient Circuit to CNF Conversion
Panagiotis Manolios, Daron Vroon 0001
SAT2
2006 Termination Analysis with Calling Context Graphs
Panagiotis Manolios, Daron Vroon 0001
CAV2
2006 Automatic memory reductions for RTL model verification
abstract
We present several techniques for automatically reducing memories in RTL designs. This includes a new memory abstraction algorithm that allows us to greatly reduce the size of memories and a technique based on-term rewriting that further improves the abstraction. In contrast to previously proposed methods for abstracting memories of RTL designs, our methods are general---e.g., they allow us to arbitrarily and directly compare memories---and they are sound and complete---e.g., there are no false positives or negatives. In addition, the combination of our techniques allows us to automatically verify RTL pipelined machine designs beyond the reach of current state-of-the-art methods, as our experimental results show.
Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001
ICCAD3
2006 Integrating static analysis and general-purpose theorem proving for termination analysis
abstract
We present emerging results from our work on termination analysis of software systems. We have designed a static analysis algorithm which attains increased precision and flexibility by issuing queries to a theorem prover. We have implemented our algorithm and initial results show that we obtain a significant improvement over the current state-of-the-art in termination analyses. We also outline how our approach, by integrating theorem proving queries into static analyses, can significantly impact the design of general-purpose static analyses.
Panagiotis Manolios, Daron Vroon 0001
ICSE2
2006 Verification Condition Generation Via Theorem Proving
John Matthews, J Strother Moore, Sandip Ray, Daron Vroon 0001
LPAR4
2005 Ordinal Arithmetic: Algorithms and Mechanization
Panagiotis Manolios, Daron Vroon 0001
J. Autom. Reason.2
2004 Integrating Reasoning About Ordinal Arithmetic into ACL2
Panagiotis Manolios, Daron Vroon 0001
FMCAD2
2003 Algorithms for Ordinal Arithmetic
Panagiotis Manolios, Daron Vroon 0001
CADE2