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D. Celi

dblp:68/88 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Electronic design automation · 33%
Theoretical computer science
1 paper
Mathematical optimization · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.011996
Extraction of SPICE BJT model parameters in BIPOLE3 using optimization methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Integrated circuit design › analog and mixed-signal circuits › device modeling
bipolar transistor modeling		 0.011996
Extraction of SPICE BJT model parameters in BIPOLE3 using optimization methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › circuit simulation
device and circuit simulation		 0.011996
Extraction of SPICE BJT model parameters in BIPOLE3 using optimization methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996

Methods — techniques the papers use, named apart from their topics

optimization methods · 0.0BIPOLE3 simulator · 0.0
YearPublicationVenuePosition
1996 Extraction of SPICE BJT model parameters in BIPOLE3 using optimization methods
abstract
We present a method for SPICE model parameter extraction for a bipolar transistor in the active and quasisaturation modes. It uses the capabilities of the BIPOLE3 simulator to enhance the optimization procedure. Comparisons are made between the Gummel-Poon, the VBIC95, and the SGS-Thomson Microelectronics SPICE model results for I/sub C/(V/sub BE/), I/sub B/(V/sub BE/), /spl beta/(I/sub C/), f/sub T/(I/sub C/), and I/sub C/(V/sub CE/) characteristics.
Alexei D. Sadovnikov, David J. Roulston, D. Celi
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3