Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive failure is incorporated resulting from rapid inflow, or outflow, of high current. Conventional modeling and simulations of the CDM are engineered to describe the behavior of ESD protection circuits, hence have a limitation to account for chip-level charge transfer. This paper presents a new methodology to simulate CDM behavior at chip level. A hierarchical approach associated with a CDM macromodel is developed to model a full-chip structure comprised of several functional subsystems and multiple power supplies. Full-chip CDM simulation provides the analysis of chip-level discharge paths and failure mechanisms, especially focusing on the gate oxide reliability. The proposed method can easily be applied to the CDM failure analysis of any product ICs in the early design stage. As an example, simulation results of a mixed-signal application-specific integrated circuit processed in a 0.25-/spl mu/m CMOS technology show high correlation with the measurement data.

A novel tool for full-chip verification is reported for CDM-ESD protection. Until recently, ESD protection has been simulated in device level, leading to the well known limitations on capturing global features such as the power protection circuits and package parasitics. In practice, fatal failures occur due to unexpected discharged paths in multi-power supply chips, which can only be verified by chip-level simulation. Associated with the new concept of macromodelling, hierarchical approach provides effective analysis methodology for mixed-signal chips. The hierarchical approach provides the analysis of chip-level discharging paths and reliability of gate oxide. Simulation results on a CMOS ASIC chip processed in a 0.25-μ technology are in accordance with the measurement data. Scanning electron microscope locates a gate oxide fault as our analysis predicted.

The design of on-chip ESD protection has become increasingly difficult and critical because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environments. A complex ESD protection network in an SoC can cause the degradation of circuit performance during normal operation. The loss introduced by ESD stress and protection networks is defined as ESD noise. In this paper, we present the generation and characterization of three different types of noise induced by ESD. The effect of ESD protection networks on sensitive circuits is investigated with a test chip processed in a 0.18 /spl mu/m CMOS technology. Experimental results suggest appropriate optimization of a tradeoff between ESD robustness and power supply coupling. It is important to note that, for mixed-signal design, the performance of a sensitive circuit is highly dependent on the ESD noise generated in the vicinity of the sensitive circuit, as well as circuit design techniques.

This paper presents S/sup 2/L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S/sup 2/L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility.