Derek Lieber

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13ranked-venue papers

0as first author

0since 2021 · last 2008

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8Software engineering, systems software and programming languages · 2Graphics, computer vision, multimedia, augmented reality and games · 1Theory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 4 papers		High-performance computing · 24% Memory systems · 21% Distributed systems · 12%
Software engineering, system software, and programming languages 3 papers		Operating systems · 34% Runtime systems and virtual machines · 26% Programming languages and type systems · 24%

Topics — the 21 heaviest of 27, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Operating systems › kernel lightweight kernel	0.1	1	2006	Blue Gene system software - Designing a highly-scalable operating system: the Blue Gene/L story · SC 2006
Memory systems › memory bandwidth memory bandwidth optimization	0.1	1	2006	Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006
Parallel and multicore computing › parallel computing › parallel communication one-sided communication	0.1	1	2006	Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006
Distributed systems › distributed communication remote memory access	0.1	1	2006	Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006
Interconnection networks and networks-on-chip › network topology torus network	0.1	1	2006	Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer · SC 2006
High-performance computing › supercomputing bluegene/l	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Memory systems › cache cache organization	0.0	1	2002	Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002
Emerging computing paradigms › unconventional computing cellular computing	0.0	1	2002	Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002
Memory systems memory hierarchy	0.0	1	2002	Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002
Processor architecture and microarchitecture multithreading	0.0	1	2002	Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002
High-performance computing supercomputing	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Processor architecture and microarchitecture › multiprocessor architecture synchronization hardware	0.0	1	2002	Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002
Integrated circuit design system-on-chip	0.0	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Programming languages and type systems method dispatch	0.0	1	2001	Efficient Implementation of Java Interfaces: Invokeinterface Considered Harmless · OOPSLA 2001
Runtime systems and virtual machines › virtual machine implementation java virtual machine	0.0	1	1999	Implementing Jalapeño in Java · OOPSLA 1999
Parallel and multicore computing parallel architecture	0.0	1	2002	Evaluation of a Multithreaded Architecture for Cellular Computing · HPCA 2002
Programming languages and type systems › object-oriented programming multiple inheritance	0.0	1	2001	Efficient Implementation of Java Interfaces: Invokeinterface Considered Harmless · OOPSLA 2001
Programming languages and type systems object-oriented programming	0.0	1	2001	Efficient Implementation of Java Interfaces: Invokeinterface Considered Harmless · OOPSLA 2001
Computational geometry › triangulation delaunay triangulation	0.0	1	1991	Efficient Delaunay Triangulation using Rational Arithmetic · ACM Trans. Graph. 1991
Computational geometry › robust geometric computation exact geometric computation	0.0	1	1991	Efficient Delaunay Triangulation using Rational Arithmetic · ACM Trans. Graph. 1991
Runtime systems and virtual machines › dynamic compilation just-in-time compilation	0.0	1	1999	Implementing Jalapeño in Java · OOPSLA 1999

Methods — techniques the papers use, named apart from their topics

linux port · 0.1compute node kernel · 0.1interrupt-driven communication · 0.1global arrays · 0.1ARMCI · 0.1system architecture design · 0.0simulation · 0.0performance scaling studies · 0.0benchmarking · 0.0dispatch table optimization · 0.0unsafe casts · 0.0reflection · 0.0magic class · 0.0rational arithmetic · 0.0adaptive-precision determinant sign computation · 0.0

Year	Publication	Venue	Position
2008	Evaluating the effect of replacing CNK with linux on the compute-nodes of blue gene/l abstract The Blue Gene machines in production today run a small single-user, single-process kernel (CNK) having a limited functionality. Motivated by the desire to provide applications with a much richer operating environment, we evaluate the effect of replacing CNK with a standard Linux kernel on the compute nodes of Blue Gene/L. We show that with a relatively small amount of effort we were able to improve benchmark performance under Linux up to a level that is comparable to CNK. Edi Shmueli, Gheorghe Almási 0001, José R. Brunheroto, José G. Castaños, Gábor Dózsa, Sameer Kumar 0001, Derek Lieber	ICS	7
2006	Blue Gene system software - Design and implementation of a one-sided communication interface for the IBM eServer Blue Gene® supercomputer abstract This paper discusses the design and implementation of a one-sided communication interface for the IBM Blue Gene/L supercomputer. This interface facilitates ARMCI and the Global Arrays toolkit and can be used by other one-sided communication libraries. New protocols, interrupt driven communication, and compute node kernel enhancements were required to enable these libraries. Three possible methods for enabling ARMCI on the Blue Gene/L software stack are discussed. A detailed look into the development process shows how the implementation of the one-sided communication interface was completed. This was accomplished on a compressed time scale with the collaboration of various organizations within IBM and open source communities. In addition to enabling the one-sided libraries, bandwidth enhancements were made for communication along a diagonal on the Blue Gene/L torus network. The maximum bandwidth improved by a factor of three. This work will enable a variety of one-sided applications to run on Blue Gene/L. Michael Blocksome, Charles Archer, Todd Inglett, Patrick McCarthy, Michael B. Mundy, Joe Ratterman, A. Sidelnik, Brian E. Smith, Gheorghe Almási 0001, José G. Castaños, Derek Lieber, José E. Moreira, Sriram Krishnamoorthy, Vinod Tipparaju, Jarek Nieplocha	SC	11
2006	Blue Gene system software - Designing a highly-scalable operating system: the Blue Gene/L story abstract Blue Gene/L is currently the world's fastest and most scalable supercomputer. It has demonstrated essentially linear scaling all the way to 131,072 processors in several benchmarks and real applications. The operating systems for the compute and I/O nodes of Blue Gene/L, are among the components responsible for that scalability. Compute nodes are dedicated to running application processes, whereas I/O nodes are dedicated to performing system functions. The operating systems adopted for each of these nodes reflect this separation of function. Compute nodes run a lightweight operating system called the compute node kernel. I/O nodes run a port of the Linux operating system. This paper discusses the architecture and design of this solution for Blue Gene/L in the context of the hardware characteristics that led to the design decisions. It also explains and demonstrates how those decisions are instrumental in achieving the performance and scalability for which Blue Gene/L is famous. José E. Moreira, Michael Brutman, José G. Castaños, Thomas Engelsiepen, Mark Giampapa, Thomas Gooding, Roger L. Haskin, Todd Inglett, Derek Lieber, Patrick McCarthy, Michael B. Mundy, Jeff Parker, Brian P. Wallenfelt	SC	9
2003	An Overview of the Blue Gene/L System Software Organization Gheorghe Almási 0001, Ralph Bellofatto, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Crumley, C. Christopher Erway, Joseph Gagliano, Derek Lieber, Xavier Martorell, José E. Moreira, Alda Sanomiya, Karin Strauss	Euro-Par	10
2003	Enabling Dual-Core Mode in BlueGene/L: Challenges and Solutions abstract BlueGene/L is a massively parallel computer system with 65536 dual-processor compute nodes. The peak performance of BlueGene/L is in excess of 360 TFLOP/s if both processor cores in a node are used for computation. The main challenge of deploying this dual-core mode of operation is that the L1 caches in each core are not hardware coherent. This forces a software-based approach to cache coherence and guides our design of a programming model for dual-core mode. We describe the design, implementation, and performance evaluation of system software for enabling the use of dual-core mode on BlueGene/L. Our preliminary performance results show that our approach to dual-core mode is effective for key numerical kernels. George S. Almási, Leonardo R. Bachega, Siddhartha Chatterjee, Manish Gupta 0002, Derek Lieber, Xavier Martorell, José E. Moreira	SBAC-PAD	5
2002	Blue Gene/L, a System-On-A-Chip abstract Summary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh	CLUSTER	38
2002	Evaluation of a Multithreaded Architecture for Cellular Computing abstract Cyclops is a new architecture for high-performance parallel computers that is being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip SMP (symmetric multiprocessor) system with multiple threads of execution, embedded memory and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper, we describe the Cyclops architecture and evaluate two of its new hardware features: a memory hierarchy with a flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40 GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high-performance systems. Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta 0002, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.	HPCA	6
2002	An overview of the BlueGene/L Supercomputer abstract This paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates	SC	53
2001	Demonstrating the scalability of a molecular dynamics application on a Petaflop computer abstract The IBM Blue Gene project has endeavored into the development of a cellular architecture computer with millions of concurrent threads of execution. One of the major challenges of this project is demonstrating that applications can successfully exploit this massive amount of parallelism. Starting from the sequential version of a well known molecular dynamics code, we developed a new application that exploits the multiple levels of parallelism in the Blue Gene cellular architecture. We perform both analytical and simulation studies of the behavior of this application when executed on a very large number of threads. As a result, we demonstrate that this class of applications can execute efficiently on a large cellular machine. George S. Almási, Calin Cascaval, José G. Castaños, Monty Denneau, Wilm E. Donath, Maria Eleftheriou, Mark Giampapa, C. T. Howard Ho, Derek Lieber, José E. Moreira, Dennis M. Newns, Marc Snir, Henry S. Warren Jr.	ICS	9
2001	Efficient Implementation of Java Interfaces: Invokeinterface Considered Harmless abstract Single superclass inheritance enables simple and efficient table-driven virtual method dispathc. However, virtual method table dispatch does not handle multiple inheritance and interfaces. This complication has led to a widespread misimpression that interface method dispatch is inherently inefficient. This paper argues that with proper implementation techniques, Java interfaces need not be a source of significant performance degradation. Bowen Alpern, Anthony Cocchi, Stephen J. Fink, David Grove, Derek Lieber	OOPSLA	5
1999	Implementing Jalapeño in Java abstract Jalape~no is a virtual machine for Java TM servers written in Java. A running Java program involves four layers of functionality: the user code, the virtual-machine, the operating system, and the hardware. By drawing the Java / non-Java boundary below the virtual machine rather than above it, Jalape~no reduces the boundary-crossing overhead and opens up more opportunities for optimization. To get Jalape~no started, a boot image of a working Jalape ~no virtual machine is concocted and written to a file. Later, this file can be loaded into memory and executed. Because the boot image consists entirely of Java objects, it can be concocted by a Java program that runs in any JVM. This program uses reflection to convert the boot image into Jalape~no's object format. A special Magic class allows unsafe casts and direct access to the hardware. Methods of this class are recognized by Jalape~no's three compilers, which ignore their bytecodes and emit special-purpose machine code. User code w... Bowen Alpern, C. Richard Attanasio, John J. Barton, Anthony Cocchi, Susan Flynn Hummel, Derek Lieber, Ton Anh Ngo, Mark F. Mergen, Janice C. Shepherd, Stephen E. Smith	OOPSLA	6
1997	Visualization of Three-Dimensional Delaunay Meshes Michael S. Karasick, Derek Lieber, Lee R. Nackman, V. T. Rajan	Algorithmica	2
1991	Efficient Delaunay Triangulation using Rational Arithmetic abstract Many fundamental tests performed by geometric algorithms can be formulated in terms of finding the sign of a determinant. When these tests are implemented using fixed precision arithmetic such as floating point, they can produce incorrect answers; when they are implemented using arbitrary-precision arithmetic, they are expensive to compute. We present adaptive-precision algorithms for finding the signs of determinants of matrices with integer and rational elements. These algorithms were developed and tested by integrating them into the Guibas-Stolfi Delaunay triangulation algorithm. Through a combination of algorithm design and careful engineering of the implementation, the resulting program can triangulate a set of random rational points in the unit circle only four to five times slower than can a floating-point implementation of the algorithm. The algorithms, engineering process, and software tools developed are described. Michael S. Karasick, Derek Lieber, Lee R. Nackman	ACM Trans. Graph.	2