The Samsung Exynos family of cores are highperformance “big” processors developed at the Samsung Austin Research & Design Center (SARC) starting in late 2011. This paper discusses selected aspects of the microarchitecture of these cores - specifically perceptron-based branch prediction, Spectre v2 security enhancements, micro-operation cache algorithms, prefetcher advancements, and memory latency optimizations. Each micro-architecture item evolved over time, both as part of continuous yearly improvement, and in reaction to changing mobile workloads.

This paper studies dirty-paper coding in a Gaussian broadcast channel with two receivers. It finds that an approximate version of dirty-paper coding using low-density lattices can be implemented with a complexity that is polynomial-time on average in the block length. The main difference between this paper and prior work is that a non-binary LDPC-based lattice codebook is used for each user, and one codebook is aligned with the other. The low-density nature enables tractable encoding and decoding algorithms, and the alignment gives structure to the overall signal transmitted and it enables us to perform the encoding and decoding efficiently.1