This article introduces G2D3, an implementation of the grammar of graphics in JavaScript, along with two practical use cases that illustrate its practicability. It makes it possible to generate interactive visualization of quantitative data in HTML/SVG. Compared to traditional static data visualization systems such as those featured in Excel and R, G2D3 makes it possible to greatly enhance the amount of conveyed information by means of animation and interaction. Compared to other JavaScript plotting libraries such as Raphaël and D3, G2D3 leverages the expressiveness and the flexibility of the grammar of graphics to concisely generate complex visualization with many plotting dimensions, including time. It makes it possible to create a wide range of graphics with a few lines of code. G2D3 is open source and hosted in GitHub: join us!

Designing for low power consumption demands power-efficient devices and good design practices to leverage the architectural features without compromising performance. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. In this paper, we are proposing a methodology for evaluating the power in three-dimensional field-programmable gate arrays (3D FPGAs) at an early stage of the design cycle namely at the partitioning step and making it a power-aware stage. As a part of the work, we also estimate the routing resources needed for the power evaluation. Our estimated power values are compared against the values obtained from a 3D place and route tool, TPR along with the added power calculations, which is demonstrating acceptable accuracy. Our results show that there is a scope for achieving desired distribution of power among the layers well before the placement with reasonable deviation in estimation and proves that our methodology is providing opportunity for power management at earlier stages of the design flow.

We introduce MAD7, a tool that rapidly simulates many-core memory architectures at a functional level. MAD7 focuses on tracking access patterns and data spatial localities rather than enforcing any precise on-chip arbitration protocols. Although not cycle accurate by nature, it provides useful insights when comparing different memory architectures under real-world workloads. Potential cache access and on-chip network usage bottlenecks can be easily spotted visually thanks to figures generated by our tool. MAD7 simulations are multi-threaded and are typically up to two orders of magnitude faster than those of a fully cycle accurate simulator.

We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart.

Three-dimensional FPGA is one of the promising innovations which can lead to the reduction in delay, area and power. There is an absolute necessity to develop algorithms and software tools to exploit the advantages of the third dimension, and to solve complex tasks associated with them. Also, thermal issues are cited as critical concern in 3D integration which results in degradation of device performance. In this paper we are proposing an idea for thermal-aware partitioning targeting the power/thermal-aware EDA flow for 3D FPGAs.

Power becomes an ever-increasing concern due to the growing design complexity and the shrinking process technology. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. Also power due to the routing resources is a dominant in field-programmable gate arrays (FPGAs). In this paper, we introduce a methodology for early estimation of hierarchical routing resources targeting power-aware EDA flow for three-dimensional FPGAs. We analyze the behavior of wire segments on a two-dimensional plane to derive a model for estimating the required number of routing segments in a 3D FPGA for a given circuit. For a number of MCNC benchmark circuits, the proposed methodology is validated against the output of TPR, an academic 3D place and route tool for FPGAs. We achieved a mean error of 29.04% for segmented wires; single-length, double-length and hex-length segments among all 14 selected benchmark circuits.

Shorter interconnects and higher integration are among the benefits that 3D die-stacking is expected to bring to future integrated circuits. However, when stacking power-dissipating dies one on top of the other, the total power density increases accordingly. As a result, temperatures in 3DICs are exacerbated. TSVs are regarded as a solution since they are made of copper and have a high thermal conductivity. In this paper, both the global and the local thermal effects of TSVs are evaluated by means of a framework based on FEM. By using a TSV grid covering a whole IC, it is shown that, on a global scale, TSVs make the overall average temperature drop slightly. Furthermore, on a local scale, it is shown that the insertion of TSVs near a hotspot has an effect that not only depends on the density of the TSVs but also on how they are arranged. Our experiments have also revealed that other parameters, such as the thermal conductivity of the material in which the hotspot is located, may influence the cooling efficiency of the TSVs.

To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is augmented to a general purpose processor to accelerate the execution of data flow graphs (DFGs) extracted from scientific applications. Procedure of mapping large DFGs onto the LSRDP is discussed and our proposed techniques for reducing area of the accelerator within the design procedure will be introduced as well.

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO*) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

In the design process of a reconfigurable accelerator employing in an embedded system, multitude parameters may result in remarkable complexity and a large design space. Design space exploration as an alternative to the quantitative approach can be employed to find a right balance between the different design parameters. In this paper, a hybrid approach is introduced to analytically explore the design space for a coarse grain accelerator and determine a wise design point exploiting data extracted from applications, quantitatively. It also provides flexibility for taking into account new design constraints as well as new characteristics of applications. Furthermore, this approach is a methodological approach which reduces the design time and results in a point which satisfies the design goals.

Application-specific instruction set extension is an effective technique for reducing accesses to components such as on- and off-chip memories, register file and enhancing the energy efficiency. However, the addition of custom functional units to the base processor is required for supporting custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies and shorter time-to-market, is becoming an issue. To address above issues, in our proposed approach, an optimized reconfigurable functional unit is used instead, and instruction set customization is done after chip-fabrication. Therefore, while maintaining the flexibility of a conventional microprocessor, the low-energy feature of customization is applicable. Experimental results show that the maximum and average energy savings are 67% and 22%, respectively for our proposed architecture framework.

To predict application performance on an HPC system is an important technology for designing the computing system and developing applications. However, accurate prediction is a challenge, particularly, in the case of a future coming system with higher performance. In this paper, we present a new method for predicting application performance on HPC systems. This method combines modeling of sequential performance on a single processor and macro-level simulations of applications for parallel performance on the entire system. In the simulation, the execution flow is traced but kernel computations are omitted for reducing the execution time. Validation on a real terascale system showed that the predicted and measured performance agreed within 10% to 20 %. We employed the method in designing a hypothetical petascale system of 32768 SIMD-extended processor cores. For predicting application performance on the petascale system, the macro-level simulation required several hours.

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problems of this approach are immense cost and long time of designing. To address these issues, an adaptive extensible processor was proposed in which custom instructions (CIs) are generated and added after chip-fabrication. To support this feature, custom functional units are replaced by a reconfigurable matrix of functional units with the capability of conditional execution. Unlike previous proposed CIs, it can include multiple exits. Experimental results show that multi-exit CIs enhance the performance by 46% in average compared to CIs limited to one basic block. A maximum speedup of 2.89 compared to a 4-issue in-order RISC processor, and a speedup of 1.66 in average, was achieved on MiBench benchmark suite

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in these systems. In older technology nodes, active power was the primary contributor to total power dissipation of a CMOS design. However, with the scaling of feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Temperature is a factor which exponentially increases the leakage current. In this paper, we show the effects of temperature on the selection of optimal cache size for low energy embedded systems. Our results show that for a given application, the optimal cache size selection is affected by the temperature. Our experiments have been done for 100nm technology. Our study reveals that the cache size selection for different temperatures depends on the rate at which cache miss increases when reducing the cache size. When the miss rate increases sharply the optimal point is the same for all examined temperatures, however when it becomes smoother, the optimal point for different temperatures begin to get farther.

The performance of collective communication operations still represents a critical issue for high performance computing systems. Users of parallel machines need to have a good grasp of how different communication patterns and styles affect the performance of message-passing applications. This paper reports our contribution of the analysis of collective communication algorithms in the context of MPI programming paradigm by extending a standard pointto- point communication model, which is P-LogP. We focus on MPI Alltoall since this function is one of the most communication intensive collective operations known. In order to reduce the gap between the predicted and the measured run-time, all the system parameters are also taken into account with the total performance estimation, by applying the linear regression modeling with the empirical data. Results on InfiniBand clusters show that the final performance prediction models can accurately capture the entire system communication behavior of all algorithms, even for large size messages and large number of processors.

This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after chip-fabrication. The custom instructions (CIs) are generated deploying the hot basic blocks during the training mode. In the normal mode, CIs are executed on the RFU. A quantitative approach was used for designing the RFU. The RFU is a matrix of functional units with 8 inputs and 6 outputs. Performance is enhanced up to 1.25 using the proposed RFU for 22 applications of Mibench. This processor needs no extra opcodes for CIs, new compiler, source code modification and recompilation.

In reconfigurable systems, reconfiguration latency is a very important factor which impact the system performance. In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for reconfigurable computing systems. A temporal partitioning algorithm is proposed which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. This algorithm attempts to find similar single or pair of operations between subsequent partitions. Considering similar pairs instead of single nodes brings about less complexity for routing process. By using this technique, smaller reconfiguration bit-stream is obtained, which directly decreases the reconfiguration overhead time at the run-time. A complementary algorithm attempts to increase the similarity of subsequent partitions by searching for similar pairs and using a technique called dummy node insertion. An incremental physical design process based on similar configurations produced in the partitioning stage improves the metrics over iterations.

We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw the patterns of circuits is a dominant factor in the manufacture time and the cost for devices. Our technique is capable of drastically reducing them by optimizing the size of characters, which are the patterns to project and are placed on CP masks. Experimental results show that our technique reduced 72.0% of EB shots in the best case, comparing with the ad hoc character sizing

This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results for avoiding unnecessary way activation in set-associative caches. The cache records tag-comparison results in an extended BTB, and re-uses them for directly selecting only the hit-way which includes the target instruction. In our simulation, it is observed that the HBTC cache can achieve 62% of energy reduction, with less than 1% performance degradation, compared with a conventional cache.

This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruction caches. The proposed cache efficiently exploits program-execution footprints recorded in the Branch Target Buffer (BTB), and attempts to detect and eliminate unnecessary tag checks at run time. Simulation results show that our approach can eliminate up to 95% of tag checks, saving the cache energy by 17%, while affecting the processor performance by only 0.2%.

We are proposing "PPRAM-Link": a new high-speed communication standard for merged-DRAM/logic SoC architecture. PPRAM-Link standard is composed of physical/logical layers and an API for the upper software layer, which are standardized by PPRAM Consortium. We developed a PPRAM-Link Interface IP family, or "PLIF Core" that realizes logical protocols necessary for subaction-level communications, and it can be applied to various applications. In addition, we designed an FPGA-based PCI-to-PPRAM-Link board for inter-PC/WS communications.

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)". The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement achieved by a direct-mapped D-VLS cache is about 27%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

Set-Associative CacheThis paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches.By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced.This paper shows that the way-predicting set-associative cache improves the ED (energy-delay) product by SO-70% compared to a conventional set-associative cache. Conventional CacheTotal energy consumed for an access to a set-associative cache ( Ecache) can be approximated by the sum of following terms [9]:

Article MOE: a special-purpose parallel computer for high-speed, large-scale molecular orbital calculation Share on Authors: Koji Hashimoto Kyushu University Kyushu UniversityView Profile , Hiroto Tomita Kyushu University Kyushu UniversityView Profile , Koji Inoue Kyushu University Kyushu UniversityView Profile , Katsuhiko Metsugi Kyushu University Kyushu UniversityView Profile , Kazuaki Murakami Kyushu University Kyushu UniversityView Profile , Shinjiro Inabata Fuji Xerox Co., Ltd Fuji Xerox Co., LtdView Profile , So Yamada Fuji Xerox Co., Ltd Fuji Xerox Co., LtdView Profile , Nobuaki Miyakawa Fuji Xerox Co., Ltd Fuji Xerox Co., LtdView Profile , Hajime Takashima Taisho Pharmaceutical Co., Ltd Taisho Pharmaceutical Co., LtdView Profile , Kunihiro Kitamura Taisho Pharmaceutical Co., Ltd Taisho Pharmaceutical Co., LtdView Profile , Shigeru Obara Hokkaido University of Education Hokkaido University of EducationView Profile , Takashi Amisaki Shimane University Shimane UniversityView Profile , Kazutoshi Tanabe National Institute of Materials and Chemical Research National Institute of Materials and Chemical ResearchView Profile , Umpei Nagashima National Institute for Advanced Interdisciplinary Research National Institute for Advanced Interdisciplinary ResearchView Profile Authors Info & Claims SC '99: Proceedings of the 1999 ACM/IEEE conference on SupercomputingJanuary 1999 Pages 58–eshttps://doi.org/10.1145/331532.331590Online:01 January 1999Publication History 2citation285DownloadsMetricsTotal Citations2Total Downloads285Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures. The basic idea is to eliminate unnecessary DRAM refreshes. We have estimated the DRAM refresh count in executing benchmark programs under several architecture models. As a result, in the most effective combination of the architectures, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most benchmark programs. In addition to it, even when we have taken normal DRAM access into account, we have obtained more than 50% reduction for several benchmarks.

This paper proposes and examines some architectural features suitable for micro-vectorprocessors. Due to the I/O-pin bottleneck, micro-vectorprocessors should save the off-chip memory bandwidth by exploiting the on-chip register bandwidth instead. Those features include the vector-instruction-level multithreading and FIFO vector registers. There are three variations of multithreading:periodic, forced, and round-robin. The paper also formulates the performance of micro-vectorprocessors with such architectural features. And then, the paper evaluates the performance attainable by those micro-vectorprocessors with such architectural features. And then, the paper evaluates the performance attainable by those micro-vectorprocessors through software simulation. From the benchmark results, it is found that the vector-instruction-level multithreading and FIFO vector registers can improve the performance of the micro-vectorprocessors with the half memory bandwidth comparable to that of ones with the full memory bandwidth. Furthermore, forced multithreading is found to be tolerant to the large memory access latency. From these results, the paper concludes that the forced multithreading at the vector-instruction level is a good candidate for the architectural features suitable to micro-vectorprocessors.

This paper presents the benchmark results on a vector-processor prototype based on the MSFV (multithreaded streaming/FIFO vector) architecture. The MSFV architecture is single-chip oriented, and thus its main object is to save the off-chip memory bandwidth by exploiting the register bandwidth instead. The register bandwidth is exploited by the synergism of FIFO register, chaining, streaming, and multithreading. This paper tries to identify the strength and weakness of those architectural features. The results for basic vector operations and Livermore Fortran Kernels are reported in terms of normalized FLOPC (floating-point operations per clock cycle) and compared to previously-reported results on the Cray X-MP, Y-MP, Fujitsu VP-200, Hitachi S-810/20, NEC SX-2, and SX-3. These comparisons show that, for many basic vector operations, the execution rate of the MSFV prototype results in worst due to its saving the memory bandwidth. However, for Livermore Fortran Kernels, the MSFV prototype results in worst due to its saving the memory bandwidth. However, for Livermore Fortran Kernels, the MSFV prototype outperforms the VP-200 by 2.11 times (geometric mean) and one processor of the X-MP by 1.22 times (geometric mean) in terms of FLOPC. Also, it is 0.67 times (geometric mean) faster than the S-810/20, and 0.76 times (geometric mean) faster than the SX-2. The paper concludes that the MSFV architecture is successful in saving the memory bandwidth.

The reconfigurable parallel processor system under development at Kyushu University is an MIMD-type multiprocessor which consists of N processing-elements (currently N is 128) fully connected by S N × N crossbar networks (currently S is 1). Each PE (Processing Element) employs a Fujitsu SPARC MB86900/10 chip-set, a Weitek WTL1164/65 chip-set, an MMU (Memory Management Unit) with 64K bytes of cache, 4M bytes of memory, and an MCU (Message Communication Unit). The modular 128 × 128 crossbar network is implemented by arranging 256 identical 8 × 8 crossbar LSI-modules in a 16 × 16 matrix form. The full 128-PE configuration achieves supercomputer levels of performance by providing 1.28 GIPS and 205 MFLOPS of computing power, 512M bytes of memory, and 2.56G bytes/s of inter-PE communication bandwidth. At the same time, it exploits unique reconfigurability in the memory and intercommunication architectures. By utilizing these two types of reconfigurability, we believe that the system can be effectively tailored to a wide spectrum of applications such as numerical computation, image processing, computer graphics, artificial intelligence, neurocomputing, and so on.

SIMP is a novel multiple instruction-pipeline parallel architecture. It is targeted for enhancing the performance of SISD processors drastically by exploiting both temporal and spatial parallelisms, and for keeping program compatibility as well. Degree of performance enhancement achieved by SIMP depends on; i) how to supply multiple instructions continuously, and ii) how to resolve data and control dependencies effectively. We have devised the outstanding techniques for instruction fetch and dependency resolution. The instruction fetch mechanism employs unique schemes of; i) prefetching multiple instructions with the help of branch prediction, ii) squashing instructions selectively, and iii) providing multiple conditional modes as a result. The dependency resolution mechanism permits out-of-order execution of sequential instruction stream. Our out-of-order execution model is based on Tomasulo's algorithm which has been used in single instruction-pipeline processors. However, it is greatly extended and accommodated to multiple instruction pipelining with; i) detecting and identifying multiple dependencies simultaneously, ii) alleviating the effects of control dependencies with both eager execution and advance execution, and iii) ensuring a precise machine state against branches and interrupts. By taking advantage of these techniques, SIMP is one of the most promising architectures toward the coming generation of high-speed single processors.