New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. The scanline algorithm virtually eliminates the redundant computation present in similar systems. It solves the VLSI layout analysis problem in O(n+k) expected time and O( square root n) expected space, where n is the total number of input segments and k is the total number of intersection points. The new scanline algorithm is robust in what it will maintain its performance over a wide range of layout styles. Experimental results show that the running time is O(n/sup 1.0547/), i.e. that these algorithms enable one to perform VLSI layout analysis in nearly linear time.>

This correspondence points out that the scope of application of the matrix model for MOS complex gates proposed by El-ziq and Su1does not cover general structures of this type. Also, an example is given to show that a complete detection test set for single stuck-at faults may not be able to detect all multiple faults in a fanout-free and irredundant MOS complex gate.

A tree representation of a combinational network is developed. An algorithm is proposed for finding the functional expression realized by the network. The tree representation has storage requirement linear with respect to the number of input-output paths in the network. It is shown that rmding the complementary function and generating network SPOOF can be performed efficiently on the tree structure.