We propose a Scene Text Recognition (STR) system for recognizing text contained in natural images. The system is comprehensive of all three steps of STR - text localization, text extraction and text recognition - making it easily applicable to mobile devices. The methods for each step are adopted and tuned from previous works to be more suitable for STR. Since STR is computationally intensive, in order to give faster results to the user, we seek to utilize the computing power of multicore processors. A multigrain parallelism method is proposed which varies the level of parallelism according to task properties and available resources during runtime. The proposed approach was tested on a set of natural scene images and an average speedup factor of 1.72 was achieved when run on a dual core processor. Our multigrain parallelism method can easily be applied to other complex image processing algorithms that work on various units of data.

In this paper, we present the design and implementation of an Open Computing Language (OpenCL) framework that targets heterogeneous accelerator multicore architectures with local memory. The architecture consists of a general-purpose processor core and multiple accelerator cores that typically do not have any cache. Each accelerator core, instead, has a small internal local memory. Our OpenCL runtime is based on software-managed caches and coherence protocols that guarantee OpenCL memory consistency to overcome the limited size of the local memory. To boost performance, the runtime relies on three source-code transformation techniques, work-item coalescing, web-based variable expansion and preload-poststore buffering, performed by our OpenCL C source-to-source translator. Work-item coalescing is a procedure to serialize multiple SPMD-like tasks that execute concurrently in the presence of barriers and to sequentially run them on a single accelerator core. It requires the web-based variable expansion technique to allocate local memory for private variables. Preload-poststore buffering is a buffering technique that eliminates the overhead of software cache accesses. Together with work-item coalescing, it has a synergistic effect on boosting performance. We show the effectiveness of our OpenCL framework, evaluating its performance with a system that consists of two Cell BE processors. The experimental result shows that our approach is promising.

Speech recognition is an important application which requires large amount of computation and data. We parallelized speech recognition on ARM11-mpcore, one of the mobile multi-core processors. We achieved 1.92 times speed-up using four cores. We argue that this is sufficiently close to the theoretical best regarding Amdahl's law. We also evaluated it on Intel Core2Quad to derive requirements for future mobile multi-core platforms.

Novel approaches to parallel H.264 decoder for symmetric multicore processors are presented. The basic partitioning of the decoder is coarse-grained and hybrid method of the data partitioning and functional partitioning. We investigate the performance bottleneck of the parallelized decoder, and propose two new approaches, software memory throttling and fair load balancing. The software memory throttling limits the number of cores involved in the parallel motion compensation to achieve better speedup and power-saving. The fair load balancing for deblocking filter reduces load imbalance caused by the conventional static partitioning method. From the evaluation on two different symmetric multicore platforms, proposed approaches show up to 24% of speedup when there is much bandwidth contention.

We propose a new method for H.264/AVC parallel decoder implementation on the CELL Broadband Engine processor. To decode the full HD H.264 stream in real time, the high performance processing is required due to the high computation and complexity. Our decoder exploits the functional partition method to parallelize the H.264 decoder on multicore platform. The load of performance critical module is dynamically balanced with less computational module to fully utilize of the multicore processors. The experimental results of proposed load balancing method show that it runs about 1.4 times faster than the normal parallel decoder with same hardware requirement - 1 PPE and 3 SPEs. This result is more than 4 times faster performance than that of the single core decoder - PPE only.

In this paper, we propose selective mode decision schemes for fast intra prediction mode selection. The objective is to reduce the computational complexity of the H.264/AVC encoder without significant rate-distortion performance degradation. In our proposed schemes, the intra prediction complexity is reduced by limiting the prediction modes with the directional information of the 16x16 prediction mode. According to the result of the 16x16 intra prediction mode, the 9 modes of the 4x4 and the 8x8 intra prediction are reduced up to 4 modes in the best case. Our proposed schemes are evaluated from the viewpoints of PSNR, bit rate, and execution time. Experimental results are presented to show that the proposed schemes reduce the complexity by up to 40% maintaining the similar PSNR quality with about 1% bit rate increase. Keywords-component; H.264/AVC, Intra prediction

Multiprocessor-system-on-a-chips (MPSoCs) are being increasingly employed to solve a diverse spectrum of problems from both high-end and low-end computing. Multimedia streaming applications can get great performance from them, but developing MPSoC software that guarantees real-time requirements is very difficult. In this paper, we present an architecture of real-time media framework that can provide both easy of programming and real-time guarantee to multimedia applications. In addition, programming model and mechanism for real-time guarantee are briefly explained. Issues in developing media framework on asymmetric MPSoC hardware further presented, which we are going to apply in our media framework implementation.

Many applications in cluster computing require QoS (quality of service) services. Since performance predictability is essential to provide QoS service, underlying systems must provide predictable performance guarantees. One way to ensure such guarantees from network subsystems is to generate global schedules from applications' network requests and to execute the local portion of the schedules at each network interface. To ensure accurate execution of the schedules, it is essential that a global time base must be maintained by local clocks at each network interface. The task of providing a single time base is called a synchronization problem and this paper addresses the problem for system area networks. To solve the synchronization problem, FM-QoS [K. Connelly (1999)] proposed a simple synchronization mechanism called FBS (feedback-based synchronization) which uses built-in flow control signals. This paper extends the basic notion of FM-QoS to a theoretical framework and generalizes it: 1) to identify a set of built-in network flow control signals for synchrony and to formalize it as a synchronizing schedule and 2) to analyze the synchronization precision of FBS in terms of flow control parameters. Based on generalization, two application classes are studied for a single switch network and a multiple switch network. For each class, a synchronizing schedule is proposed and its bounded skew is analyzed. Unlike FM-QoS, the synchronizing schedule is proven to minimize the bounded skew value for a single switch network. To understand the analysis results in practical networks, skew values are obtained with flow control parameters of Myrinet-2000. We observed that the maximum bounded skew of FBS is 5.79/spl mu/sec or less over all our experiments. Based on this result, we came to a conclusion that FBS was a feasible synchronization mechanism in system area networks.

The complexity and dynamic nature of the Internet (and the emerging Computational Grid) demand that middleware and applications adapt to the changes in configuration and availability of resources. However, to the best of our knowledge there are no simulation tools which support systematic exploration of dynamic Grid software (or Grid resource) behavior. We describe our vision and initial efforts to build tools to meet these needs. Our MicroGrid simulation tools enable Globus applications to be run in arbitrary virtual grid resource environments, enabling broad experimentation. We describe the design of these tools, and their validation on micro- benchmarks, the NA parallel benchmarks, and an entire Grid application. These validation experiments show that the MicroGrid can match actual experiments within a few percent (2% to 4%).