Demo Data from SIGIR 2026 / reviewers in the wild / expert
Bo Lei 0005
dblp:71/3606-5
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0001-3159-2614ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 62% Memory systems · 38% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
computation offloading |
0.7 | 1 | 2023 | A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures · ACM Trans. Archit. Code Optim. 2023 |
Compilers and program optimization › accelerator compilation
heterogeneous compilation |
0.7 | 1 | 2023 | A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures · ACM Trans. Archit. Code Optim. 2023 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
in-memory computing accelerator |
0.7 | 1 | 2023 | A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures · ACM Trans. Archit. Code Optim. 2023 |
Memory systems
non-volatile memory |
0.2 | 1 | 2023 | A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures · ACM Trans. Archit. Code Optim. 2023 |
Memory systems › non-volatile memory
resistive memory |
0.2 | 1 | 2023 | A Compilation Tool for Computation Offloading in ReRAM-based CIM Architectures · ACM Trans. Archit. Code Optim. 2023 |
Methods — techniques the papers use, named apart from their topics
pattern identification · 1.3LLVM compiler infrastructure · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | A Compilation Tool for Computation Offloading in ReRAM-based CIM ArchitecturesabstractComputing-in-Memory (CIM) architectures using Non-volatile Memories (NVMs) have emerged as a promising way to address the “memory wall” problem in traditional Von Neumann architectures. CIM accelerators can perform arithmetic or Boolean logic operations in NVMs by fully exploiting their high parallelism for bit-wise operations. These accelerators are often used in cooperation with general-purpose processors to speed up a wide variety of artificial neural network applications. In such a heterogeneous computing architecture, the legacy software should be redesigned and re-engineered to utilize new CIM accelerators. In this article, we propose a compilation tool to automatically migrate legacy programs to such heterogeneous architectures based on the low-level virtual machine (LLVM) compiler infrastructure. To accelerate some computations such as vector-matrix multiplication in CIM accelerators, we identify several typical computing patterns from LLVM intermediate representations , which are oblivious to high-level programming paradigms. Our compilation tool can modify accelerable LLVM IRs to offload them to CIM accelerators automatically, without re-engineering legacy software. Experimental results show that our compilation tool can translate many legacy programs to CIM-supported binary executables effectively, and improve application performance and energy efficiency by up to 51× and 309×, respectively, compared with general-purpose x86 processors. Hai Jin 0001, Bo Lei 0005, Haikun Liu, Xiaofei Liao, Zhuohui Duan, Chencheng Ye 0001, Yu Zhang 0027 |
ACM Trans. Archit. Code Optim. | 2 |