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Tsutomu Hosaka

dblp:71/4078 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 75% Parallel and multicore computing · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing
parallel algorithms		 0.011983
A Parallel Processing Approach for Logic Module Placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › placement
parallel placement		 0.011983
A Parallel Processing Approach for Logic Module Placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation
physical design		 0.011983
A Parallel Processing Approach for Logic Module Placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design
placement		 0.011983
A Parallel Processing Approach for Logic Module Placement · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983

Methods — techniques the papers use, named apart from their topics

two-dimensional processor array · 0.0adjacent pairwise exchange · 0.0
YearPublicationVenuePosition
1983 A Parallel Processing Approach for Logic Module Placement
abstract
A parallel processing algorithm for logic module placement is presented. Conventionally, such placement problems have been solved on a single processor in a sequential manner. In this paper, it is shown that a two-dimensional processor array structure can be applied to the placement problem, resulting in a substantial reduction of the processing time. This parallel processing algorithm is based on the concept that the adjacent pairwise exchange method could be expanded to the parallel processing case. By using simulation programs, it is shown that the placement results obtained by the parallel processing algorithm are a little better than those obtained by the sequential algorithm. In addition, the theoretical estimations in respect to the processing cycle iterations correspond well with the simulation results.
Kazuhiro Ueda, Tsutomu Komatsubara, Tsutomu Hosaka
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3