Methods are presented for generating bounds on interconnection delays in a combinational network having specified timing requirements at its input and output terminals. An automatic placement program that uses wirability as its primary objective could use these delay bounds to generate length or capacitance bounds for interconnection nets as secondary objectives. Thus, unlike previous timing-driven placement algorithms, the desired performance of the circuit is guaranteed when a wirable placement meeting these objectives is found. Fast algorithms are provided that maximize the delay range, and hence the margin for error in layout, for various types of timing constraint.>

Vanguard is a new physical design system which combines advantages of gate array and custom design methods to produce high-density chips on non-custom regular images. Vanguard physically partitions a chip into subchips which define macro boundaries and which contain not only macro circuitry and internal macro wires but also inter-macro connections and portions of connections which are part of the final chip design and lie within that region. Subchips are individually designed and then connected by abutment to assemble the chip. Vanguard has been used to design a 32-bit DCVS microprocessor comprising 13 macros, including a large register array.

Differential cascode voltage switch (DCVS) trees are high performance, high functionality CMOS circuits, which, because they have a large number of inputs and internal connections, are difficult to wire on a large scale. Wirability is substantially improved by local customization at the tree level. This paper describes a DCVS customization procedure that exploits the fact that a Boolean function has more than one physical realization. Using ACORN, an automated physical design system based on this concept, we have placed and wired several designs, the largest of which is a group of three interconnected macros comprising approximately 800 DCVS trees.

In this paper, a problem in macro design using cascode-switch tree logic is studied. It involves selecting specific tree instantiations of Boolean functions and input variable assignments to maximize the alignment of variables between adjacent trees. An algorithm to find optimal solutions based on the principle of optimality is proposed. Although in general it is not a polynomial time algorithm, it runs sufficiently fast for our practical application. Finally we prove the problem is NP-complete, thus the existence of polynomial time algorithms is indeed unlikely.