This paper presents our work on improving an existing density-based clustering algorithm. By using Bayesian sequential partitioning (BSP) in the density estimation part of the algorithm, we were able to significantly reduce the computational complexity of the clustering algorithm. Simulation results showed 15 to 40% reduction in computation time, depending on the dimensions of the data, while retaining the clustering accuracy of the original algorithm.

Non-parametric density estimation methods are more flexible than parametric methods, due to the fact that they do not assume any specific shape or structure for the data. Most non-parametric methods, like Kernel estimation, require tuning of parameters to achieve good data smoothing, a non-trivial task, even in low dimensions. In higher dimensions, sparsity of data in local neighborhoods becomes a challenge even for non-parametric methods. In this paper, we use the copula transform and two efficient non-parametric methods to develop a new method for improved non-parametric density estimation in multivariate domain. After separation of marginal and joint densities using copula transform, a diffusion-based kernel estimator is employed to estimate the marginals. Next, Bayesian sequential partitioning (BSP) is used in the joint density estimation.

A single supply CMOS non-inverting level shifter circuit, ccm-ls, for converting input signals from 0.3V up to 0.7V is presented. The circuit is optimized and pre-layout simulated in a 65nm CMOS process technology. At the target design voltage of 0.3V, the level shifter has a propagation delay of 1.06ns, an energy consumption of only 0.79pJ, and energy-delay product of 0.84pJns for capacitive load of lpf. Simulation results are compared to other similar published works at a frequency of 500 MHz, and it shown that the proposed circuit outperforms them.

This paper presents an algorithm for efficient multivariate density estimation, using a blockized implementation of the Bayesian sequential partitioning algorithm. We also present a method for improving the performance of the blockized density estimation, by progressively updating the partitions. With progressive partitioning algorithm, each block uses the results from the previously processed blocks, and thus, as the simulation results show, it improves the performance of the blockized algorithm, both in terms of estimation accuracy and computation time.

This paper presents an algorithm for density estimation over non-stationary high-dimensional data streams. It is based on a blockized implementation of the Bayesian sequential partitioning (BSP) algorithm. We discuss how to decide the optimum block size, based on features of the stream, the application requirements, and the available resources. Simulation results are presented to show the applicability of the proposed method to non-stationary streams. It is also shown that the proposed framework satisfies the general design criteria for systems with the mission of online machine learning and data mining over data streams.

Cooperation among sensors in a wireless sensor network, deployed for industrial monitoring in an indoor scenario, is a topic of interest in the smart factory and smart city research. The indoor wireless communication channel is very harsh and the observations of all the sensors cannot be sent reliably to the base station. Failure to transmit correct sensing results to the base station may result in false alarms or missed detection of events. Therefore, we propose a cooperation scheme for the wireless sensors to send the data reliably to the base station. Our aim is to increase the reliability of the received information, reduce the probability of error, lower the overall power consumption, and keep the latency to an acceptable low level. We propose a reliability factor feedback algorithm to adjust the weight of unreliable sensors in the decision‐making process. The proposed scheme is analyzed based on its latency, power consumption, and packet delivery ratio. Our results show significant improvement in the reliability of the received data, improved packet delivery, and reduced false alarm ratio for full repetition and cluster head‐based cooperation. The power consumption and latency in data transmission are also kept to an acceptable low level.

A single supply CMOS up level shifter (rsc-ls), for upconverting signals from 0.45V-0.9V logic level range up to 1V power supply voltage domain (Vdd), is introduced. From simulations results, the proposed shifter provides improvements of 63% and 69% in energy consumption and speed, respectively, when compared with a similar design, in 65nm CMOS process and low threshold voltage. For a Vdd of 1.2V we obtain up to 88% improvement in delay-energy product, when the input signal high voltage level is 0.7V with a frequency of 500MHz. We report a total static current reduction of up to 110 times. For an up shift of 0.45V to 1.2V at an output loading of 800fF, our design offers a delay of 0.38ns and an energy consumption of 1.57pJ.

The rich choice of hierarchical partitioning modes within the coding tree unit (CTU) in the high efficiency video coding (HEVC/H.265) standard is the main reason for its higher coding efficiency, as well as its high computational complexity. The single most timing consuming process in H.265/HEVC is motion estimation (ME). In this paper, to accelerate the ME process, we propose an efficient parallel algorithm by exploiting inter-pixel similarity. The result shows with less than 1% bitrate increases ME can be accelerated by up to 5.7 times. To further enhance the encoder performance, we propose a novel strategy that employs quantization parameter as the indicator to early-terminate the coding. Overall encoding time is improved by up to 3.5 times, with a less than 6% increase in the bitrate.

Density estimation is a fundamental part of statistical analysis and data mining. In high-dimensional domains, parametric methods and the commonly used non-parametric methods like histograms or Kernel estimators fail to perform properly. In this paper, we present computationally efficient data structures for efficient implementation of the Bayesian sequential partitioning (BSP), as a framework for density estimation in high-dimensional domain. Simulation results are presented to analyze the performance for large high-dimensional datasets.

This paper investigates the problem of MVC from a high-level perspective and proposes a multiple-view-frame-parallel (MVFP), scheduling scheme for a computing cluster. The proposed scheme outperforms the view sequential coding by a factor of more than 12, for the IPP prediction structure for MVC.

In this paper, we propose a novel massively parallel motion estimation for HEVC using an efficient yet flexible predicate algorithm, ScalingFast that exploits inter-pixel similarities. When evaluated over four video test video sequences with changing resolution, the proposed algorithm outperforms the anchor algorithm by factor of up to 4.6, with little to no loss in rate-distortion (RD) performance.

The challenge to H.265/HEVC multiview video coding (MVC) is its extremely high computational complexity. This paper presents the development and implementation of a scalable massively parallel fast search algorithm to significantly reduce the computational cost of motion and disparity estimation over the current best available GPU full block matching and sub optimal CPU fast search algorithms by a factor up to 2.4 and 8.4, respectively.

Many high dimensional data mining applications involve the nearest neighbor search (NNS) on a KD-tree. Randomized KD-tree forest enables fast medium and large scale NNS among high dimensional data points. In this paper, we present massively parallel algorithms for the construction of KD-tree forest, and NNS on a cluster equipped with massively parallel architecture (MPA) devices of graphical processing unit (GPU). This design can accelerate the KD-tree forest construction and NNS significantly for the signature of histograms of orientations (SHOT) 3D local descriptors by factors of up to 5.27 and 20.44, respectively. Our implementations will potentially benefit realtime high dimensional descriptors matching.

Multiview video coding (MVC) has recently received considerable attention. It is proposed as an extension of H.264/Advanced Video Coding (AVC) standard for multiple video source compression. To resolve the extremely high computational complexity of MVC (and in fact other AVC techniques), suitable parallel algorithms need to be developed that are amenable to implementation on low-cost massively parallel architecture, platforms that have found a common place due to recent advances in the parallel computer architecture. The high complexity of MVC is due to its prediction structure, where motion estimation (ME) between the frames and disparity estimation (DE) between the views contribute to more than 99% of overall complexity of the coder. This paper presents the development and implementation of a scalable massively parallel fast search algorithm to significantly reduce the computational cost of ME/DE over the current best available full block matching, and suboptimal fast search algorithms. The proposed massively parallel fast search algorithm (DZfast), when evaluated over eight views, outperforms the existing full search and fast search MVC algorithms by a factor of up to 245.8 and 8.4, respectively. This speedup comes at no or minute loss in rate-distortion performance.

This paper presents the use of a computer cluster with heterogeneous computing components to provide concurrency and multi-level parallelism at coarse grain and massive fine-grain for multiview video coding (MVC) applications. MVC involves coding of multiple video sequences that are taken from the same scene but different perspective. In addition to motion estimation (ME) used in conventional video coding for single view video for exploiting inter-frame temporal similarities, MVC adopts disparity estimation (DE) to further increase compression. To overcome the huge computational cost associated with ME and by extension with DE, attention has been mainly focused on developing fast ME/DE algorithms. Although fast ME/DE algorithms bring substantial speedup, to achieve realtime MVC encoding, it requires further acceleration of the coding process at higher levels. Towards this end, this paper proposes a multiple-view-parallel, multiple-interleaved group of pictures (multiple-IGOP) scheduling scheme for MVC. When evaluated over eight views, with no loss in rate distortion (RD) performance, the proposed scheme outperforms view-sequential coding by a factor of up to 12.4 and 12.3, respectively, for two popular prediction structures, IBP and IPP.

This paper presents parallel algorithms for the construction of k dimensional tree (KD-tree) and nearest neighbor search (NNS) on massively parallel architecture (MPA) of graphics processing unit (GPU). Unlike previous parallel algorithms for KD-tree, for the first time, our parallel algorithms integrate high dimensional KD-tree construction and NNS on an MPA platform. The proposed massively parallel algorithms are of comparable quality as traditional sequential counterparts on CPU, while achieve high speedup performance on both low and high dimensional KD-tree. Low dimensional KD-tree construction and NNS algorithms, presented in this paper, outperform their serial CPU counterparts by a factor of up to 24 and 218, respectively. For high dimensional KD-tree, the speedup factors are even higher, raising to 30 and 242, respectively. Our implementations will potentially benefit real time three-dimensional (3D) image registration and high dimensional descriptor matching.

In this paper we investigate the complexity of a modified MQ arithmetic decoder architecture for error resilient JPEG2000 applications, based on the concept of ternary arithmetic decoder employing a forbidden symbol. Such ternary coding schemes have been already investigated to prove its excellent figures in terms of both PSNR and visual quality. However the complexity of the modified MQ decoder and its impact on real implementations has not been considered yet. In this paper an architectural analysis is performed and an optimized architecture is proposed.

Multiview video coding (MVC) is an extension of H.264/AVC standard. Its purpose is to further increase compression efficiency when multiple video sources are presented for coding. The computational complexity of MVC, however, is extremely high due to the motion estimation (ME) between the frames and disparity estimation (DE) between the views, contributing to more than 99% of overall complexity of the coder. For MVC to find a common place for real-time applications requires acceleration of ME and DE engines. On the other hand, there is a recent uptake of graphical processing unit (GPU) computing to significantly enhance the performance of signal and image processing applications, through massive-parallel processing. This paper presents the development and GPU implementation of a parallel full search algorithm to significantly reduce the computational complexity of ME and DE over the full search and TZsearch estimations on a sequential processor, by a factor of 300 and 4, respectively.

RaptorQ code, the next generation of Raptor code for forward error correction (FEC), is proposed to significantly reduce the redundant information. However, the improved coding performance comes at the expense of increased encoding and decoding complexity. On the other hand, graphics processing units (GPUs) are finding their way beyond graphics processing into general purpose computing in the consumer market. This paper investigates the suitability of GPU for RaptorQ code to process large block and symbol sizes in FEC transmission. The paper explores serial and parallel implementations of Raptor code on CPU and GPU, respectively. Our work shows that efficient parallelization on the GPU can improve the performance of the decoder significantly. Furthermore, simulations are performed for the practical real time requirement in multimedia broadcast/multicast service (MBMS) and digital video broadcasting (DVB) in highspeed downlink packet access (HSDPA) network. Conclusions are drawn with respect to the applicability of this new code for realtime multimedia broadcasting and content delivery on GPU.

Multiple input multiple output (MIMO) techniques are widely employed in modern wireless systems. The most prominent approaches to MIMO communication are space–time coding (STC) and spatial multiplexing (SM). Less studied is a hybrid technique called adaptive MIMO switching (AMS), which may be employed by fixing the transmission rate and selecting between space–time block coding and SM transmission modes based on instantaneous channel conditions to achieve the most efficient link. This study presents a hardware implementations of a selector algorithm and a detector employing it. The detector is designed for a 2×2 MIMO system and was implemented on an Altera Cyclone II FPGA. In addition, two transmission protocols with decision feedback from the receiver to the transmitter via a low-rate feedback channel are introduced and the feasibility of switching for high-data-rate transmissions is discussed.

Current trends constantly increase the need for ultra-low power solutions for the embedded and portable hard ware. One circuit component required in wide range of devices is the analog-to-digital converter (ADC). In this paper we propose an extremely energy-efficient successive approximation register (SAR) ADC, in which we have overcome the limitations of conventional approaches through topological improvements. Further, advances include a novel bootstrapped track and hold (T/H) circuitry. Statistical simulations indicate an ADC with a figure of merit (FOM) of 11.9 fJ per conversion step, and an effective number of bits (ENOB) of 9.2, operating close to Nyquist frequency, sampling at 1 Msps. To put it into perspective, consuming only 7 pJ/sample, this ADC is able to work at its maximum speed for more than 40 years with the total energy of a single alkaline AA battery.

Raptor codes have been proven very suitable for mobile broadcast and multicast multimedia content delivery, and yet their computational complexity has not been investigated in the context of embedded systems. At the heart of Raptor codes are the matrix inversion and vector decoder operations. This paper analyzes the performance, energy profile, and resource implication of two matrix inversion and decoding algorithms; Gaussian elimination (GE) and third Generation Partnership Group (3GPP) standard (SA), for the Raptor decoder on a system on a chip (SoC) platform with a soft-core embedded processor. We investigate the effect of the cache size, memory type, and mapping on the performance of the two algorithms under consideration. We show that with an appropriate data to memory mapping, a speedup factor of 5.77 can be obtained for GE with respect to SA. This paper also proposes a dedicated peripheral hardware block that achieves 5.90 times better performance compared with the software, requiring an energy consumption that is lower by a factor of 5.5, when the symbol size and the data path word length are small (32 bits). We show that with parallel processing in hardware, using the wider word lengths, and employing bigger symbol sizes T, we can improve the performance, while reducing the energy consumption. Extending the hardware word length and symbol size T to 128 bits will result in a performance improvement factor of 6.73 in favor of the hardware; while energy consumption reduces by a factor of 3.8.

In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implementation in an embedded processor. We demonstrate the superiority of our proposed architecture in terms of performance (by a factor 12), power and energy dissipation (by a factor of 15). We also include the hardware resource requirements in the comparison. Furthermore, the proposed hardware architecture is parameterized and easily scalable. The data processing word size has been successfully extended up to 1024 bits and fitted within the chosen FPGA hardware platform.

This paper presents a novel detector implementation that takes advantage of instantaneous channel states by switching between Space-Time Coding (STC) and Spatial Multiplexing (SM) modes. For a fixed rate, the detector calculates whether the channel is better suited for SM or STC transmission. This decision can then be fed back to the transmitter via a low-rate feedback channel. The detector is designed for a 2 × 2 multiple-input multiple-output (MIMO) system and implemented on an Altera Cyclone II FPGA.

This paper presents the design of a highly area efficient bootstrapped CMOS level shifter (vj-level shifter). The proposed vj-level shifter uses a single bootstrap capacitor to minimise active area and to maintain the voltage difference between the gates of output pull-up PMOS and output pulldown NMOS transistors. When implemented on a 65 nm CMOS technology, under the large capacitive loading condition (2pF), vj-level shifter has a lower active area (93%), and energy-delay product (15%) than the reference level shifter circuit (ts-level shifter). Also vj-level shifter has very small effective input capacitance in comparison with ts-level shifter because the first does not need extra bootstrap capacitor connected with the input.

This paper presents the design of a highly efficient CMOS 2-input NAND (gcr-nand). When implemented on a 65 nm CMOS technology, under 1 pF capacitive loading condition, gcr-nand has a lower active area (3.4 times lower), and energy-delay product (56%) than the reference 2-input NAND (lscpl-nand). Furthermore, gcr-nand is able to operate under a high output load.

This paper presents the design of an adiabatic/bootstrapped CMOS driver (xb-ad) using complementary pass-transistor logic (CPL) and a four-phase power clock. The proposed xb-ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65 nm CMOS IV technology, under the large capacitive loading condition (16pF), xb-ad performs better than the reference adiabatic circuit (cpl-ad) in terms of active area (64%), and energy-delay product (39%). Moreover, xb-ad supports 10 times higher output capacitive load without any additional circuit sizing than cpl-ad.

This paper proposes for the first time, the very large scale integration (VLSI) architectural techniques for error resilient joint source channel coding (JSCC) of arithmetic codes (AC). When implemented on a 0.13 ¿m standard cells technology running at 340 MHz, achieves a decoding throughput of up to 125 kbit/s, 58 times better than the standard implementation.

Coupling capacitance between adjacent wires in on-chip busses significantly increases the average transition energy dissipation. This paper develops a mathematical model for a memoryless encoding scheme and proposes a novel partitioning method for reducing the transition energy. Specifically, for an 8-bit bus in 65 nm CMOS technology, we present an 11-wire solution that reduces energy dissipation by 22%. The proposed scheme achieves similar energy efficiency without increasing the complexity of the encoding and decoding circuitry when the bus is extended to 16, 32 and 64 bits.

This paper presents the design and comparative evaluation of four low energy CMOS adiabatic drivers; ib-drive using a dual-rail structure with complementary input and output; scal-driver using a single input stage based on a single transistor driving a pair of cross-coupled CMOS inverters; ob-driver using an output stage with two inverters driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells; ee-driver using an output stage with two bootstrap capacitors driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13µm CMOS 1.0V technology, ib-driver performs better than the other adiabatic circuits, in terms of the energy-delay product by up to 68%.

Coupling capacitance between adjacent wires in on-chip interconnect significantly increases the average transition energy dissipation, and the maximum delay. This paper proposed a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Specifically for 65nm CMOS technology, we present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, and delay by 24%, without any additional area penalty, while requiring a less complex circuit overhead when compared with transition pattern coding (TPC) scheme.

Much work has been performed on optimizing the throughput of the block coding system within JPEG2000. However, the question remains as to whether providing parallel simple block coders provides a cheaper method of increasing throughput than complicated optimized block coders. We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We design both a simple and a high performance, optimized peripheral encoder as a hardware accelerator for the JPEG2000 SoC encoding system. The system is implemented on an Altera NIOS II processor with flexible integrated peripheral. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks, and that parallel optimized encoders outperform parallel simple encoders. We also demonstrate that the block coding system becomes work starved rather than memory blocked when many parallel coders are present, indicating a discrete wavelet transform bottleneck.

Features of the JPEG2000 compression standard include coding efficiency at low bit rates. However, its compressed bit stream is sensitive to transmission error. This paper presents three techniques to reduce both the computational complexity and the memory requirement in the ternary MQ arithmetic decoding. Such coders introduce a controlled degree of redundancy during the encoding process, which can be exploited at the decoder side in order to detect and correct errors. Our proposed techniques result in a substantial saving of decoding time and memory usage, with no or little degradation in the PSNR metric.

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-$\mu$m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). Themj-sibandmj-dbschemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.

To improve the JPEG2000 compression standard error resiliency in the wireless environment, the use of ternary MQ arithmetic coders/decoders that are based on the concept of forbidden symbol has been proposed. This paper presents two ternary MQ based techniques to reduce both the computational complexity and the memory requirement during the decoding process, with no or little degradation in the PSNR.

Discrete wavelet transform (DWT) and embedded block coder (BC) are two main modules in JPEG2000 compression system. Data transfer between the DWT and BC modules presents challenges due to difference in data format generated by the DWT and data format required by the BC module. In this paper, we investigate data transfer and storage techniques between the DWT and BC modules. We propose an efficient memory organization and data transfer schemes to reduce the data bandwidth. A VLSI architecture for the proposed data transfer system is proposed and synthesized for TSMC 0.18- process. Simulation results show that our proposed techniques result in approximately four times less bandwidth for the BC module while requiring an extra hardware cost of only 11%.

We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks. The system was implemented on an Altera NIOS II processor with flexible integrated peripheral.

This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj-driver) suitable for driving of global interconnects with large capacitive load. When implemented on 0.13μm CMOS technology,mj-driverperforms 16% faster, reduces the power consumption by 3%, and energy delay product by 19% when compared with a counterpart driver in diode-connected configuration. On the other hand,mj-driverhas 47% lower active area and only requires one set of sizing for optimum performance at 1 and 0.8V. Furthermore, unlike its counter part which exhibits 30% variation in output swing voltage with variation in the load, the output voltage swing for the proposed driver remains unchanged with the output load. Comparisons of the proposed driver with conventional full swing CMOS driver are presented as well, indicating a significant saving in energy, due to the reduced swing voltage. The proposed driver has the ability to switch from a low swing to high swing mode, through a line monitoring mechanism.

JPEG2000 is a new image compression standard known for its rich set of features, impressive compression performance as well as its complexity for efficient hardware implementation. Discrete Wavelet Transform (DWT) and embedded Block Coder (BC) are two main modules in JPEG2000 compression system. Data transfer between the DWT and BC modules presents challenges due to difference in data format generated by the DWT and data format accepted by the BC module. This paper investigates data transfer and storage techniques between the DWT and BC modules. The paper proposed an efficient memory organization and a data transfer scheme to reduce the data bandwidth. A VLSI architecture for the proposed data transfer (DT) system is proposed and synthesized for TSMC 0.18μm process. Simulation results show that the proposed techniques result in an aggregate reduction in the bandwidth requirement by a factor of four for the BC module while incurring an extra hardware cost of only 5%.

Optimal rate-control is an important feature of JPEG2000 which allows simple truncation of compressed bit stream to achieve best image quality at a given target bit rate. Accurate distortion estimation (DE) with respect to the allowed bit stream truncation points, is essential for the rate-control performance. In this paper, we address the issues involved in accurate DE for the hardware oriented implementation of JPEG2000 encoding systems. We propose a novel hardware efficient DE technique. Rate control based on the proposed technique results in a average peak signal-to-noise ratio degradation of only 0.02 dB with respect to the optimal DE technique used in the software implementations of JPEG2000. This is the best performance reported in comparison to existing techniques. The proposed technique requires only an additional 4096 memory bits per block coder which is 80% less than the memory requirements of optimal technique.

This paper reports a high speed and low power consumption direct-indirect bootstrapped full-swing CMOS inverter driver circuit (bfi-driver). The simulation results, based on 0.13mum triple well CMOS technology, show that, when operated at IV, bfi-driver is 94% faster and consumes 22% less power compared to a counterpart direct bootstrap circuit (Bellaour, 1995)

Optimal rate-control is a very important feature of JPEG2000 which allows simple truncation of compressed bit-stream to achieve best image quality at a given target bit-rate. Accurate distortion estimation with respect to allowed bit-stream truncation points, is essential for rate-control performance. In this paper, we address the issues involved in accurate distortion estimation for hardware oriented implementation of JPEG2000 encoding systems with generic block coding capabilities. We propose a novel hardware friendly distortion estimation technique. Rate control based on the proposed technique results in only an average 0.02 dB PSNR degradation with respect to the optimal distortion estimation approach used in the software implementations of JPEG2000. This is the best performance reported in comparison to existing techniques. The proposed technique requires only an additional 4096 bits per block coder which is 80% less than the memory requirements of optimal approach

This paper presents the VLSI architecture for the V-BLAST detection for a 4 times 4 16-QAM MIMO wireless communication systems based on the QR factorization technique. We present the design and optimization of the pre decoder block based on the CORDIC rotator processors. We also present the architecture of the back substitution symbol interference cancellation (SIC) block that eliminates the need for division and multiplication, thereby substantially, reducing the hardware cost, without compromising the numerical stability. The proposed VLSI architecture is implemented on an Altera Stratix FPGA. A detection throughput of 149 Mb/s is achieved on this platform. This paper also investigates the use of a parallel decoding scheme to improve the BER performance

The block coder, which is a key module in the JPEG2000 image compression system, presents challenges for realization of a high-throughput, low-hardware-cost VLSI architecture. Though efficient architectures have been proposed for a block coder operating in specific modes, existing generic block coder architectures have low throughput versus hardware cost performance. In this paper, we present a low-cost, high-throughput VLSI architecture for a generic block coder. Concurrent symbol processing (CSP) is used to improve throughput of the block coder's submodules, the bit plane coder (BPC) and arithmetic coder (AC). The proposed BPC processes one stripe-column/clock-cycle during every coding pass and generates up to 10 context-data (CxD) pairs/clock-cycle. The proposed AC processes two CxD/clock-cycles. Throughput is then further increased by using column speedup and novel run-mode skipping techniques at the BPC module. Hardware cost for the proposed block coder is reduced by using an optimal two-subbank BPC memory architecture. Additionally, image statistics are used to choose efficient configuration parameters for the VLSI architecture. The proposed block coder is implemented on Altera stratix FPGA and TSMC ASIC 0.18-mum platforms. Implementation results show that our block coder has average throughputs of 16.23 and 73.42 Msamples/s, respectively, on the FPGA and ASIC platforms. The block-coder test chip has 22515 gates and 2.33 mm2chip area. In comparison with similar existing architectures, it has the highest throughput versus hardware cost performance

A single phase latch (SPL) suitable for GaAs domino logic gates and compatible with DCFL is presented. Two versions of the SPL are reported in this work: single ended SPL used in pure domino logic and differential SPL used in dynamic cascode voltage switch logic. SPL is compared with other common GaAs dynamic circuits and latches. The results demonstrate that SPL is superior in terms of device count, area, clock rate and power consumption.

In this paper design of fast arithmetic circuits using a GaAs based feed through logic (FTL) family is presented. A modified version of FTL termed differential FTL (DFTL) is introduced and basic aspects of design methodologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of device count, chip area, delay clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators.