This paper proposes Harmoni, a high performance hardware accelerator architecture that can support a broad range of run-time monitoring and bookkeeping functions. Unlike custom hardware, which offers very little configurability after it has been fabricated, Harmoni is highly configurable and can allow a wide range of different hardware monitoring and bookkeeping functions to be dynamically added to a processing core even after the chip has already been fabricated. The Harmoni architecture achieves much higher efficiency than software implementations and previously proposed monitoring platforms by closely matching the common characteristics of run-time monitoring functions that are based on the notion of tagging. We implemented an RTL prototype of Harmoni and evaluated it with several example monitoring functions for security and programmability. The prototype demonstrates that the architecture can support a wide range of monitoring functions with different characteristics. Harmoni takes moderate silicon area, has very high throughput, and incurs low overheads on monitored programs.

Recently, researchers have proposed decoupled monitoring architectures that utilize parallel hardware such as multi-cores or accelerators to enable fine-grained security and reliability checks with low overheads. However, today's decoupled monitoring architectures lack support for precise exceptions and can only detect an exception after the monitored program completes an erroneous operation. In this paper, we present an architectural mechanism to support precise exceptions in nonspeculative processors with decoupled monitors. Experimental results based on an RTL implementation show that our approach has low area, power, and performance overheads even when applied to simple, in-order processors.

This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a large class of software attacks can be detected by running multiple versions of a program simultaneously and checking the consistency of their behaviors. However, execution of multiple replicas incurs significant overheads on today's computing platforms, especially with fine-grained comparisons necessary for high security. Orthrus exploits similarities in automatically generated replicas to enable simultaneous execution of those replicas with minimal overheads; the architecture reduces memory and bandwidth overheads by compressing multiple memory spaces together, and additional power consumption and silicon area by eliminating redundant computations. Utilizing the hardware architecture, Orthrus implements a fine-grained memory layout diversification with the LLVM compiler and can detect corruptions in both pointers and critical data. Experiments indicate that the Orthrus architecture incurs minimal overheads and provides a protection against a broad range of attacks.

Today, incorporating a new hardware feature into a modern microprocessor is a highly time consuming and expensive process due to long design cycles and high costs of design and verification. To address this challenge, this paper proposes a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with a processing core. A new hardware feature for fine-grained run-time monitoring can be implemented on the FPGA fabric without requiring a re-design or a fabrication of a chip. To evaluate this FPGA co-processing approach, we implemented Dynamic Information Flow Tracking (DIFT), which is arguably one of the most powerful security features against software attacks, on the FPGA fabric. The synthesis and performance emulation results demonstrate that DIFT on the FPGA fabric adds relatively small area and power consumption to a modern microprocessor while providing the performance that is close to the performance of a custom hardware DIFT implementation.

This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into a modern microprocessor, the Flex Core architecture allows parallel monitoring and bookkeeping functions to be dynamically added to the processing core and adapt to application needs even after the chip has been fabricated. At the same time, Flex Core is far more efficient than software implementations because its fine-grained reconfigurable architecture closely matches bit level operations of typical monitoring schemes and allows monitoring schemes to operate in parallel to the monitored core. In fact, our experimental results show that monitoring on Flex Core can almost match the performance of full ASIC implementations. To evaluate the Flex Core architecture, we implemented an RTL prototype along with several extensions including uninitialized memory read checking, dynamic information flow tracking, array bound checking, and soft error checking. The prototypes demonstrate that the architecture can support a range of monitoring extensions with different characteristics in an efficient manner. Flex Core takes moderate silicon area and results in far better performance and energy efficiency than software.

This paper proposes a novel approach to check the authenticity of hardware based on the inevitable performance gap between real hardware and simulations or emulations that impersonate it. More specifically, we demonstrate that each processor design can be authenticated by requiring a checksum incorporating internals of complex micro-architectural mechanisms to be computed within a time limit; this checksum is different for each processor model and only authentic secure hardware can obtain the checksum fast enough. This new authentication approach provides attractive solutions to privacy, scaling, and security issues of traditional approaches that otherwise rely only on certificates. Architectural simulations and an RTL implementation show that the proposed approach is viable with very low hardware overheads.