This paper describes the design of an ultra low power CMOS PLL clock synthesizer targeting wireless sensor applications that require low minimum power dissipation. Based on integer-N architecture, the PLL clock synthesizer produces a 100 kHz output signal from a reference input signal generated using an on-chip crystal oscillator operating at 32.768 kHz. Fabricated in a 0.6-μm N-well CMOS process technology, the PLL achieves a power consumption of 20 μW with a frequency accuracy of ±13 Hz.

This paper describes the design of a CMOS PLL clock synthesizer targeting biomedical applications in the 20-400 MHz range. Based on integer-N architecture, the synthesizer produces a 400-mV LVDS output signal swing on a 1.2 V common mode level under 50-Ω load. Fabricated in a 0.35-μm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-psrmsand 38-psppat 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The phase noise response has a peak of -115 dBc/Hz at the loop bandwidth.

A three-terminal network consisting of two matched tunnel diodes and a fixed resistor is introduced as a basic element for performing peak threshold summation logic. The characteristic between two terminals resembles a tunnel diode curve where application of a signal or bias current to the third terminal causes reduction of the observed peak current. Decrease of this peak current below a fixed load line allows switching from the low- to the high-voltage state for logic-function circuit operation. Such bias-controlled tunnel pairs are shown to be unilateral to a considerable extent (30 db). This is advantageous in logic networks since it allows directional flow of information without the provision of multiphase power supplies or backward diodes, as needed in conventional tunnel diode logic circuits to eliminate back-switching. Circuits are described based on this principle, consisting entirely of tunnel junctions and resistors, for performing OR, MAJORITY, AND and NOR logic. Generalized design equations for circuits with a fan-in of M and a fan-out of N are derived. Test circuits based upon the generalized equations with a fan-in of 9 and a fan-out of 5 were found to operate over a temperature range from -70° to +60°C. A sample switching speed measurement for an OR gate using 1-ma tunnel diodes and a normal degree of drive showed a 7.5-nsec rise time which was triple that observed with a single tunnel diode under similar conditions.