Content Addressable Memory (CAM) is beneficial to applications that require high-speed pattern searching as it provides fast associative lookup operations. As the amount of data to search continues to grow, reducing power consumption while minimizing the costs for speed and area is the main thread of research in designing large capacity CAMs. In this work, we are presenting an active memory architecture incorporating a searchable resistive memory. The proposed architecture incorporates processing logic in close proximity to the RRAM and the RRAM-based TCAM, where the unit TCAM cell is comprised of five transistors and two memristors. Analyzed and simulated performance (e.g., latency, energy consumption, and storage density) of the RRAM-based TCAM at various technology nodes are presented and compared to those of prior CAM/TCAM designs.

New memristors-based resistive logic computation units are introduced. By controlling the memristors' conditional set operation adaptively to one of the input polarities, bipolar signal multiplication of an input and a stored reference bit is performed by unipolar memristor devices and control switches. The multiplication result is registered in an output nonvolatile memristor so that the computed output can be accessed anytime later on by reading the output memristor's state. The memristive multiplier circuits demonstrate a fast correlation computing for highly complex inputs.

In this paper, a 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n x m passive memory arrays of memristive devices. This data-dependent 2 × 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 × 128 passive array with OFF-to-ON resistance ratio of 103.

This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarity written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.

This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with limited resistance ranges, a simple method to find their constitutive relationships is discussed, and examples of compact models are shown for both current-controlled and voltage-controlled memristors. Our models satisfy all of the memristor properties such as frequency dependent hysteresis behaviors and also unique boundary assurance to simulate memristors whether they behave memristively or resistively. Our models are implementable in circuit simulators, including SPICE, Verilog-A, and Spectre.