Demo Data from SIGIR 2026 / reviewers in the wild / expert
Lawrence C. Widdoes Jr.
dblp:72/4949
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1978
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Integrated circuit design · 31% Electronic design automation · 31% Processor architecture and microarchitecture · 31% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › digital circuit design
logic design |
0.0 | 1 | 1978 | SCALD: Structured Computer-Aided Logic Design · DAC 1978 |
Electronic design automation
physical design |
0.0 | 1 | 1978 | The SCALD physical design subsystem · DAC 1978 |
Processor architecture and microarchitecture
multiprocessor architecture |
0.0 | 1 | 1976 | The Minerva Multi-Micropocessor · ISCA 1976 |
Interconnection networks and networks-on-chip › bus-based interconnection
bus architecture |
0.0 | 1 | 1976 | The Minerva Multi-Micropocessor · ISCA 1976 |
Processor architecture and microarchitecture › exception handling
interrupt handling |
0.0 | 1 | 1976 | The Minerva Multi-Micropocessor · ISCA 1976 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1978 | SCALD: Structured Computer-Aided Logic Design
Thomas M. McWilliams, Lawrence C. Widdoes Jr. |
DAC | 2 |
| 1978 | The SCALD physical design subsystem
Thomas M. McWilliams, Lawrence C. Widdoes Jr. |
DAC | 2 |
| 1976 | The Minerva Multi-MicropocessorabstractA multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. Lawrence C. Widdoes Jr. |
ISCA | 1 |