TCP/IP is too slow for scaled AI interconnect •Bound by CPU SW kernel

Vision, Path Planning, Auto-Labeling

The Samsung Exynos family of cores are highperformance “big” processors developed at the Samsung Austin Research & Design Center (SARC) starting in late 2011. This paper discusses selected aspects of the microarchitecture of these cores - specifically perceptron-based branch prediction, Spectre v2 security enhancements, micro-operation cache algorithms, prefetcher advancements, and memory latency optimizations. Each micro-architecture item evolved over time, both as part of continuous yearly improvement, and in reaction to changing mobile workloads.

The AMD Jaguar x86 core uses a fully-synthesized, 128-bit native floating-point unit (FPU) built as a co-processor model. The Jaguar FPU supports several x86 ISA extensions, including x87, MMX, SSE1 through SSE4.2, AES, CLMUL, AVX, and F16C instruction sets. The front end of the unit decodes two complex operations per cycle and uses a dedicated renamer (RN), free list (FL), and retire queue (RQ) for in-order dispatch and retire. The FPU issues to the execution units with a dedicated out-of-order, dual-issue scheduler. Execution units source operands from a synthesized physical register file (PRF) and bypass network. The back end of the unit has two execution pipes: the first pipe contains a vector integer ALU, a vector integer MUL unit, and a floating-point adder (FPA), the second pipe contains a vector integer ALU, a store-convert unit, and a floating-point iterative multiplier (FPM). The implementation of the unit focused on low-power design and on vectorized single-precision (SP) performance optimizations. The verification of the unit required complex pseudo-random and formal verification techniques. The Jaguar FPU is built in a 28nm CMOS process.

This paper describes the architecture and physical design of the AMD Bobcat x86 microprocessor core-C6 (CC6) sleep state. Each core and dedicated 512KB L2 cache use control flows to save and restore the x86 architectural state in concert with a network of PFET sleep transistors that drive an internal voltage domain. Measured results show an approximate 92% reduction in leakage power at the cost of 1-3% die area with a 31μs restore latency. Each core and L2 cache pair use 98cm of total sleep transistor width in a TSMC 40nm bulk CMOS process.

A new floating-point fused multiply-add (FMA) design for the execution of (A times B) + C as a single instruction is presented. The bridge fused multiply-add unit is a design intended to add FMA functionality to existing floating-point coprocessor units by including specialized hardware that reuses floating-point adder and floating-point multiplier components. The bridge unit adds this functionality without requiring an overhaul of coprocessor control units and without degrading the performance or parallel execution of addition and multiplication single instructions. To evaluate the performance, area, and power costs of adding a bridge FMA unit to common floating-point execution blocks, several circuits including a double-precision floating-point adder, floating-point multiplier, classic FMA, and a bridge FMA unit have been designed and implemented with AMD 65-nm silicon-on-insulator technology to provide a realistic and fair analysis of the presented FMA hardware tradeoffs.