Demo Data from SIGIR 2026 / reviewers in the wild / expert
M. A. Canto
dblp:73/2484
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 2 | 1982 | An Upper Bound for the Synthesis of Generalized Parallel Counters · IEEE Trans. Computers 1982 Synthesis of Generalized Parallel Counters · IEEE Trans. Computers 1981 |
Integrated circuit design › digital circuit design › arithmetic circuit design
parallel counter |
0.0 | 2 | 1982 | An Upper Bound for the Synthesis of Generalized Parallel Counters · IEEE Trans. Computers 1982 Synthesis of Generalized Parallel Counters · IEEE Trans. Computers 1981 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | An Upper Bound for the Synthesis of Generalized Parallel CountersabstractRecently, an algorithm has been developed for synthesizing generalized parallel counters (GPC's) with a network of smaller ones [11]. In this correspondence we obtain an upper bound q, for the number of levels q in the synthesis of GPC's. This upper bound generalizes and improves the values deduced by other authors in [13] and [14]. Sebastián Dormido 0001, M. A. Canto |
IEEE Trans. Computers | 2 |
| 1981 | Synthesis of Generalized Parallel CountersabstractSynthesis of generalized equal column parallel counters from smaller ones is presented. The notation used for a general counter is (n × N; d), where n is the number of input columns, N is the number of input bits in each column, and d = s · n (s = 2, 3,···) is the number of bits in the output word. Sebastián Dormido 0001, M. A. Canto |
IEEE Trans. Computers | 2 |