3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack

This paper describes computational techniques for concurrent Direct Simulation Monte Carlo (DSMC) of neutral flow inside three-dimensional plasma reactors. These techniques are designed to reduce the overall time to obtain realistic three-dimensional results. A simulation problem is first defined by automatically generating a tetrahedral grid. This grid is statically partitioned in order to achieve scalable memory utilization. Parallel algorithms allow high-performance multicomputer architectures to be leveraged to reduce simulation time. Adaptive gridding techniques are employed to maintain the desired accuracy in the presence of dynamic flow variations. Load balancing algorithms, based on heat diffusion, are used to maximize efficiency. Finally, automatic granularity control is used to ensure appropriate granularity for load balancing and for maximum processor utilization. Simulation results are presented for a simulation of the GEC reference cell in a flow configuration of industrial relevance. Performance results are presented for large-scale multicomputers, symmetric multiprocessors and networks of PCs. Copyright © 2000 John Wiley & Sons, Ltd.