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Richard P. Williams

dblp:73/6264 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Processor architecture and microarchitecture · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › arithmetic unit
arithmetic unit design
0.011977
Serial Integer Arithmetic with Magnetic Bubbles · IEEE Trans. Computers 1977
Integrated circuit design › emerging device technologies
magnetic bubble logic
0.011977
Serial Integer Arithmetic with Magnetic Bubbles · IEEE Trans. Computers 1977
Integrated circuit design › digital circuit design
logic gate design
0.011977
Serial Integer Arithmetic with Magnetic Bubbles · IEEE Trans. Computers 1977

Methods — techniques the papers use, named apart from their topics

pipeline design · 0.0
YearPublicationVenuePosition
1977 Serial Integer Arithmetic with Magnetic Bubbles
abstract
The logical operation of two-input bubble gates is described. All logical interactions use bubble repulsion to prevent bubbles from transferring to an adjacent path. This principle unifies the gate design and is intended to facilitate hardware development. The serial nature of bubble technology is used to best advantage with pipeline structures. Two-input gates are employed to produce relatively simple pipeline designs for serially adding, subtracting, multiplying, and dividing binary integers. The size of the division unit is reduced by adapting the pipeline circuit for recursive operation. The compactness of these designs is demonstrated by a circuit layout exercise using standard propagation patterns for 6 μ bubbles. The small areas required for the bubble arithmetic units should make them competitive with semiconductors for a class of real time signal processing applications requiring modest throughput rates.
Richard P. Williams
IEEE Trans. Computers1