Demo Data from SIGIR 2026 / reviewers in the wild / expert
Mary P. Bivens
dblp:73/6894
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Debugging and program repair · 100% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Debugging and program repair › software debugging
debugging optimized code |
0.0 | 1 | 1994 | Debugging Optimized Code Via Tailoring (Abstract) · ISSTA 1994 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Debugging Optimized Code Via Tailoring (Abstract)abstractNo abstract available. Lori L. Pollock, Mary P. Bivens, Mary Lou Soffa |
ISSTA | 2 |
| 1990 | Incremental Register ReallocationabstractAbstract Current compiler technology performs extensive code transformations either to parallelize code or to perform optimizations that reduce space or time. The cost of the analyses for these transformations is high and is further magnified when edits are made, forcing complete recompilation. By extending the concept of incremental compilation to include fine‐grained, high‐quality target code generation, we develop techniques that reuse the information created by an optimizing compiler to incorporate program edits efficiently into optimized target code. Our techniques include developing models of register usage for both local and global register allocation schemes and algorithms for incrementally updating these structures in response to an editing change. Based on these changes, the target code is updated. As graph colouring is a widely accepted register allocation scheme, we present techniques to rebuild and recolour interference graphs incrementally. Results from experiments that compare the performance of the incremental target code generator with its non‐incremental counterpart are reported, showing a saving when incorporating changes incrementally. Mary P. Bivens, Mary Lou Soffa |
Softw. Pract. Exp. | 1 |