Neuromorphic Continual Learning (NCL) paradigm leverages Spiking Neural Networks (SNNs) to enable continual learning (CL) capabilities for AI systems to adapt to dynamically changing environments. Currently, the state-of-the-art employ a memory replay-based method to maintain the old knowledge. However, this technique relies on long timesteps and compressiondecompression steps, thereby incurring significant latency and energy overheads, which are not suitable for tightly-constrained embedded AI systems (e.g., mobile agents/robotics). To address this, we propose Replay4NCL, a novel efficient memory replaybased methodology for enabling NCL in embedded AI systems. Specifically, Replay4NCL compresses the latent data (old knowledge), then replays them during the NCL training phase with small timesteps, to minimize the processing latency and energy consumption. To compensate the information loss from reduced spikes, we adjust the neuron threshold potential and learning rate settings. Experimental results on the class-incremental scenario with the Spiking Heidelberg Digits (SHD) dataset show that Replay4NCL can preserve old knowledge with Top-1 accuracy of $\mathbf{9 0. 4 3 \%}$ compared to $\mathbf{8 6. 2 2 \%}$ from the state-of-the-art, while effectively learning new tasks, achieving 4.88x latency speed-up, $\mathbf{2 0 \%}$ latent memory saving, and 36.43% energy saving. These results highlight the potential of our Replay4NCL methodology to further advances NCL capabilities for embedded AI systems.

Traditional learning-based approaches for runtime hardware Trojan (HT) detection require complex and expensive on-chip data acquisition frameworks, and thus incur high area and power overhead. To address these challenges, we propose to leverage the power correlation between the executing instructions of a microprocessor to establish a machine learning (ML)-based runtime HT detection framework, called MacLeR. To reduce the overhead of data acquisition, we propose a single power-port current acquisition block using current sensors in time-division multiplexing, which increases accuracy while incurring reduced area overhead. We have implemented a practical solution by analyzing multiple HT benchmarks inserted in the RTL of a system-on-chip (SoC) consisting of four LEON3 processors integrated with other IPs, such as vga_lcd, RSA, AES, Ethernet, and memory controllers. Our experimental results show that compared to state-of-the-art HT detection techniques, MacLeR achieves 10% better HT detection accuracy (i.e., 96.256%) while incurring a 7× reduction in area and power overhead (i.e., 0.025% of the area of the SoC and <; 0.07% of the power of the SoC). In addition, we also analyze the impact of process variation (PV) and aging on the extracted power profiles and the HT detection accuracy of MacLeR. Our analysis shows that variations in fine-grained power profiles due to the HTs are significantly higher compared to the variations in fine-grained power profiles caused by the PVs and aging effects. Moreover, our analysis demonstrates that on average, the HT detection accuracy drops in MacLeR is less than 1% and 9% when considering only PV and PV with worst case aging, respectively, which is ≈10× less than in the case of the state-of-the-art ML-based HT detection technique.

The success of deep learning has fast paced the evolution of current technology at unprecedented rate. In particular, deep convolutional neural networks (CNNs) has gained a lot of attention due to their extraordinary performance in a wide range of computer vision applications. While the performance of CNNs has been excellent, their implementation complexity has, however, always posed a challenge due to their computational and memory access intensive nature of CNNs especially for resource constrained embedded platforms. In this paper, we propose a novel reduced-parameter CNN architecture that can be used for image classification applications, which results in a significant network model size reduction. Our reduction method, inspired by SqueezeNet, replaces convolutional layer kernels with smaller sized kernels and removes all the fully connected layers other than the last classifying layer. The proposed architecture results in less computational complexity when deployed in hardware. We implemented the proposed architecture by fitting all trained network parameters on-chip using Xilinx Vivado targeting Zynq XC7Z020-1CLG484C FPGA device. The proposed architecture has 11.2× less parameters and has an improvement of 2.8× Area-Delay Product, compared to LeNet, resulting in an efficient hardware deployment.

The recent advancements in system-on-chip (SoC) and network-on-chip (NoC) have enormously increased the number of on-chip frequency domains that are originating from multiple on-chip clock sources. In modern battery-operated internet of things (IoT) devices, limited power budget and requirement for complex clock distribution schemes increases the usage clock multipliers. These multiple clock signal requirements are usually catered for by using frequency multipliers with clock generators. However, most of these multipliers are based on analog components that require a customized layout, involve timing uncertainties, and are power hungry and highly prone to mismatches in the process variations and environmental changes. Moreover, in modern battery-operated smart devices for IoT have very limited power budget, which makes the design of clock multipliers even more challenging. To address these issues, we propose a delay-based digital frequency multiplier, which uses 2-input XNOR gates and a true single-phase clock (TSPC) flip-flop because of pulse generation and edge detection properties, respectively. The proposed multiplier is based on the digital components, therefore, it reduces the power consumption significantly, i.e., 1.6mW, which is almost 50% lesser than other low power state-of-the-art designs. Moreover, it can operate for a wide range of input frequencies, ~400MHz to 1GHz. The Monte-Carlo simulation results are very promising as they indicate the robustness of the design against process and environmental variations.

Globalization trends in integrated circuit (IC) design are leading to increased vulnerability of ICs against hardware Trojans (HT). Recently, several side channel parameters based techniques have been developed to detect these hardware Trojans that require golden circuit as a reference model, but due to the widespread usage of IPs, most of the system-on-chip (SoC) do not have a golden reference. Hardware Trojans in intellectual property (IP)-based SoC designs are considered as major concern for future integrated circuits. Most of the state-of-the-art runtime hardware Trojan detection techniques presume that Trojans will lead to anomaly in the SoC integration units. In this paper, we argue that an intelligent intruder may intrude the IP-based SoC without disturbing the normal SoC operation or violating any protocols. To overcome this limitation, we propose a methodology to extract the power profile of the micro-controllers instruction sets, which is in turn used to train a machine learning algorithm. In this technique, the power profile is obtained by extracting the power behavior of the micro-controllers for different assembly language instructions. This trained model is then embedded into the integrated circuits at the SoC integration level, which classifies the power profile during runtime to detect the intrusions. We applied our proposed technique on MC8051 micro-controller in VHDL, obtained the power profile of its instruction set and then applied deep learning, k-NN, decision tree and naive Bayesian based machine learning tools to train the models. The cross validation comparison of these learning algorithm, when applied to MC8051 Trojan benchmarks, shows that we can achieve 87% to 99% accuracy. To the best of our knowledge, this is the first work in which the power profile of a microprocessor's instruction set is used in conjunction with machine learning for runtime HT detection.

Single clock distribution over a large high performance chip can be very challenging. This led to evolution of globally asynchronous and locally Synchronous (GALS) systems in modern deep sub-micron (DSM) technology. In GALS mostly bundled data protocols which are based on handshake mechanism, are used for data transfer. But these protocols rely on timing assumptions between handshake signals and data values that causes timing closure problems, which poses strict constraints in system-on-chip (SoC) design. This work leverages quasi delay insensitive (QDI) designs to propose GALS design templates. This will facilitate the use of GALS systems in a conventional digital design flow with minimal intervention to interfacing modules. Modifications for two different quasi delay insensitive (QDI) asynchronous designs have been suggested, implemented and verified by using the proposed templates. Power, energy and latency have been compared for two different interfaces.

Globalization trends in integrated circuit (IC) design using deep submicron (DSM) technologies are leading to increased vulnerability of ICs against malicious intrusions. These malicious intrusions are referred as hardware Trojans. One way to address this threat is to utilize unique electrical signatures of ICs. However, this technique requires analyzing extensive sensor data to detect the intruded integrated circuits. In order to overcome this limitation, we propose to combine the signature extraction mechanism with machine learning algorithms to develop a self-learning framework that can detect the intruded integrated circuits. The proposed approach applies the lazy, eager or probabilistic learners to generate self-learning prediction model based on the electrical signatures. In order to validate this framework, we applied it on a recently proposed signature based hardware Trojan detection technique. The cross validation comparison of these learner shows that eager learners are able to detect the intrusion with 96% accuracy and also require less amount of memory and processing power compared to other machine learning techniques.

We present a new Charge Based Capacitance Measurement (CBCM) CMOS sensor for Lab-on-Chip applications. This integrated capacitive sensor consists of a fully differential capacitance to voltage converter, a sigma delta (ΣΔ) modulator, and interdigitated electrodes realized on top metal layer in 0.35 µm CMOS process. The proposed CMOS capacitive sensor offers higher dynamic-range (10 fF) and sensitivity (350 mV/fF) in comparison to our previously reported core-CBCM capacitive sensors. We proved this significant improvement by demonstrating the chemical solvent concentration measurements and discussing the potential applications in environmental monitoring and water safety applications.

Abstract In a wireless network, mutual secure neighbor verification (MSN) is defined as the capability of a node (verifier) to verify the claim by another node (claimer) that it exists within a certain physical distance from the verifier. This problem has received great attention because it has numerous practical applications. Current state‐of‐the‐art approaches to solve this problem, such as the use of time of flight, signal strength, and angle of arrival, suffer from impracticality in terms of application and computation cost. In this work, we propose two algorithms to mitigate the MSN problem during the incremental deployment phase of static senor networks. Each node should announce its location and the power level it uses for transmission. Cooperative and base station verifications are used to detect nodes that lie about their locations. The simulation results show that we can achieve high detection (>90%) of nodes that forge their location information using either high power transmission or by colluding with other malicious nodes. Copyright © 2011 John Wiley & Sons, Ltd.

In this paper, we propose an antenna selection algorithm for down link MIMO SDMA OFDM system. For each user, the data rate corresponding to each transmit antenna is maximized using the optimal bit loading algorithm. A data rate matrix is constructed and used for the antenna selection algorithm assuming the base station (BS) knows the signal-to-noise ratio on all antenna-user pairs of all sub-carriers. In addition to exploiting the multi-user diversity gain, all users are served fairly by the BS. The fairness is achieved through weighting the data rate matrix by a weighting matrix with coefficients inversely proportional to the number of times served for each user. Jain's fairness index is used as a measure of the fairness. Simulation results show that a significant increase in the data rate is a achieved compared to the ultimately fair round Robin algorithm, while satisfying a reasonable fairness.

The field of remote health monitoring now includes technologies such as home and mobile health monitoring, tele-retinal imaging, tele-radiology, remote cardiac monitoring, video conferencing and sensors for remote diagnosis and treatment to patients. In this regard, implantable wireless body sensor networks (IWBSNs) have recently emerged as an important and growing research area. These implantable sensors are required to be reliable, very small, battery-operated, and capable of collecting data, processing it, and transmitting it wirelessly and efficiently. Since these devices are required to run with limited resources (energy, processing, and memory), their utility protocols (collecting, processing, and communication) should be designed carefully, not only to work reliably but, more importantly, to be resource-efficient. The life time of the embedded batteries associated with these sensor nodes varies from a few days to a few weeks as was described in a previous work by the authors. In this paper, we propose a novel technique which allows the implanted sensor nodes to communicate with a base station located outside the body efficiently by consuming the minimum amount of energy. Our proposed protocol allows the battery to last significantly longer even for years with a gain of up to 100's times of power saving. This will improve the quality of patient life, and reduce risk of infection resulting from frequent chirurgical operations needed to replace such implantable batteries. Also, a new time synchronization algorithm is briefly introduced in this work that is especially applicable to our proposed communication protocol.

Repeaters are now widely used to enhance the performance of long On-Chip interconnects in CMOS VLSI. For RC-modeled interconnects, parallel repeaters have proved to be superior to serial ones. In this paper, a Variable-Segment Regeneration Technique is introduced and compared with a Variable-driver Parallel Technique, a recently proposed transparent repeater and with three conventional techniques. HSpice Simulations using a 0.25 μm TSMC technology show that both the variable-segment and variable-driver techniques feature 62% time delay saving and 354% Area-Delay product saving over the transparent repeater, and are superior to all conventional techniques. However, our new variable-segment technique is characterized by a 116% Area-Delay product saving over the variable-driver technique. Thus, making it the most performant in the field of high-performance RLC interconnect regeneration. The simulation results confirm the superiority of the parallel regeneration technique over the serial ones.