Previously, communications in parallel programs for High Performance Computing (HPC) and Distributed Computing (DC) are mostly written with two-sided communication interfaces that are based on a pair of operations, Send and Receive. Since such interface requires explicit synchronization between both sides of the communication, techniques for communication optimization such as overlapping are not efficiently described in many cases. On the other hand, one-sided communication interface is becoming important as a method to describe asynchronous communications to enable highly overlapped communication with computation. As one of such interface, in this demonstration, Advanced Communication Primitives (ACP) is introduced. ACP is a portable interface that supports UDP, IBverbs of InfiniBand and Tofu library of K Computer. In addition to that, it is designed to be memory efficient. For example, with 10 thousand processes, the memory consumption of ACP over UDP is estimated to be less than 1MB. Since the number of computational elements is increasing more rapidly than the amount of available memory, this memory efficiency is becoming one of the keys for parallel programs in HPC and DC. To show this characteristics, we run ACP library on Raspberry Pi 2, and examine its performance and memory consumption.

Network simulation is an important technique for designing interconnection networks and communication libraries. Also network simulations are useful for the analysis of internal communication behavior in parallel applications. This paper introduces a new interconnection network simulator NSIM-ACE. This simulator enables us to evaluate RDMA directly while existing simulators do not have such capability. NSIM-ACE also provides a similar user-interface to RDMA-based parallel programs for easy use. The experimental evaluation indicates that the simulation accuracy is sufficient to compare performance of some RDMAbased algorithms and the simulator is capable of predicting performance scalability for non-extinct networks.

To predict application performance on an HPC system is an important technology for designing the computing system and developing applications. However, accurate prediction is a challenge, particularly, in the case of a future coming system with higher performance. In this paper, we present a new method for predicting application performance on HPC systems. This method combines modeling of sequential performance on a single processor and macro-level simulations of applications for parallel performance on the entire system. In the simulation, the execution flow is traced but kernel computations are omitted for reducing the execution time. Validation on a real terascale system showed that the predicted and measured performance agreed within 10% to 20 %. We employed the method in designing a hypothetical petascale system of 32768 SIMD-extended processor cores. For predicting application performance on the petascale system, the macro-level simulation required several hours.

This work presents a dynamically reconfigurable platform called EXPRESS-1, which uses the commercially available embedded processor FPGA. The system makes the most of a fully reconfigurable logic part to explore the area of fine-grained reconfigurable computing. A dynamic reconfiguration mechanism is implemented utilizing a real-time operating system, so device reconfiguration in response to application demand works without suspending other services. EXPRESS-1 features a transparent execution mechanism. Whether a function is executed by the hardware or software, the mechanism frees users from awareness of its execution manner. Furthermore, there is no need to explicitly specify reconfiguration commands into a program because the system determines if reconfiguration is needed based on current conditions. The development of EXPRESS-1 and the runtime reconfiguration mechanism of the fully reconfigurable logic are described. System capabilities are also reported through fundamental evaluations with some practical applications such as JavaVM, encryption processing, and image processing.