The exponential growth of the Internet of Things (IoT) in the 5G era has significantly heightened the demand for secure communication among numerous edge devices. While lattice-based cryptography has gained prominence as a quantum-resistant alternative to traditional public-key cryptosystems vulnerable to quantum attacks, its high computational complexity remains a critical barrier for resource-constrained IoT edge devices. In this paper, we propose a configurable and efficient public-key cryptographic circuit architecture that achieves an optimal area-performance balance through three key innovations. First, we introduce a parameter-adaptive coefficient generation unit that compresses hash round constants, thereby reducing circuit redundancy and memory overhead. Second, we present a four-channel even-odd parallel butterfly operation architecture, with collaborative optimization of the butterfly unit (BFU) and data storage scheme. Finally, we optimize data flow scheduling between functional modules under resource constraints, significantly enhancing circuit compactness and bandwidth utilization. FPGA prototyping on the Xilinx Artix-7 platform demonstrates that the Kyber-1024 process is completed in just 11.75k clock cycles, while the hardware efficiency improvements range from 1.2× to 7.3× over existing state-of-the-art designs, maintaining an excellent area-performance trade-off. ASIC implementation using SMIC 40nm CMOS technology achieves a 332MHz operating frequency, with hardware efficiency improvements ranging from 6.3× to 57× compared to recent implementations. Therefore, this work establishes a new paradigm for deploying post-quantum cryptography in latency-sensitive IoT applications.

The Paillier scheme, widely recognized as the most prevalent additive homomorphic encryption paradigm, faces significant challenges in Internet of Things (IoT) applications due to latency, power, and hardware overhead. This paper proposes an efficient Paillier homomorphic encryption circuit for IoT, integrating Chinese Remainder Theorem (CRT) acceleration. First, we propose an algorithm framework tailored for hardware reuse that supports multiple functionalities of the Paillier scheme. It introduces an Montgomery modular multiplication (MMM) algorithm with superior Area-Time Product (ATP) to implement core computations, and reduces hardware cost by reusing MMM to replace other computational units. Then, a computational unit reuse architecture based on the algorithmic framework is designed to reduce resource overhead. Moreover, a split-coupled MMM circuit design is proposed to counteract computational resource expansion induced by CRT operations. The hardware design is synthesized under SMIC 40 nm CMOS technology. The evaluation shows that the proposed scheme provides a high-performance Paillier circuit design with less area and lower power, offering an effective solution for data security processing in IoT.

We propose a generalized convolutional neural network (CNN) architecture that first decomposes the input signal into subbands by an adaptive filter bank structure, and then uses convolutional layers to extract features from each subband independently. Fully connected (FC) layers finally combine the extracted features to perform classification. The proposed architecture restrains each of the subband CNNs from learning using the entire input signal spectrum, resulting in structural regularization. Our proposed CNN architecture is fully compatible with the end-to-end learning mechanism of typical CNN architectures and learns the subband decomposition from the input dataset. We show that the proposed CNN architecture has attractive properties, such as robustness to input and weight-and-bias quantization noise, compared to regular full-band CNN architectures. Importantly, the proposed architecture significantly reduces computational costs, while maintaining state-of-the-art classification accuracy. Experiments on image classification tasks using the MNIST, CIFAR-10/100, Caltech-101, and ImageNet-2012 datasets show that the proposed architecture allows accuracy surpassing state-of-the-art results. On the ImageNet-2012 dataset, we achieved top-5 and top-1 validation set accuracy of 86.91% and 69.73%, respectively. Notably, the proposed architecture offers over 90% reduction in computation cost in the inference path and approximately 75% reduction in back-propagation (per iteration) with just a single-layer subband decomposition. With a two-layer subband decomposition, the computational gains are even more significant with comparable accuracy results to the single-layer decomposition.

The Internet of Things (IoT) has demonstrated promising growth, as it is crucial to numerous application domains in smart ecosystems, such as the smart city. Decentralization can help achieve growth, with previous research proposing the use of the decentralized blockchain technology in IoT ecosystems as, among others, it can offer cryptographically trustworthy interactions, nonrepudiable smart contracts, and interoperability between stakeholders. However, proposals are often theoretical or very specific to IoT ecosystem subareas, for instance, healthcare. In both cases, implementation may not be feasible in a larger ecosystem. This article investigates the performance, particularly throughput, aspect of feasibility. It proposes and demonstrates a platform that uses the blockchain technology as a building block in an IoT ecosystem. A permissioned blockchain network is built, performance is measured, and the measurements are interpreted in a smart city context, thus, providing valuable insights about real-world implementations and their degree of feasibility.

New healthcare record management (HRM) systems have been introduced as technology has evolved to provide more efficient care. Since medical data is usually sensitive and must be protected from unauthorized access, attention must be paid to data integrity, patient privacy, and storage. Blockchain technology has been proposed in the literature to integrate healthcare information systems through a decentralized and unified network. However, the literature on blockchain in healthcare is full of promises that may not be true under certain conditions. In our paper, we evaluate the veracity and sophistication of some of the claims made in the literature. We go beyond performing a literature review and shed light on the weak technical aspects claimed about blockchain. In addition, we benefit from our technical assessment and suggest some future research directions to improve healthcare systems that use blockchain and big data solutions.

Although blockchain was proposed in 2008 to solve the centralization problem in information exchange and eliminate the need for trusted third parties such as intermediaries or banks to conduct financial transactions, private blockchain applications today still suffer from the centralization problem. This situation has arisen because we cannot manage metadata on private or public blockchains, but a representation of this data as hashes or key values when the metadata is registered on central servers or the cloud. In this study, we highlight two decentralized storage platforms (IPFS and Sia) that can solve the centralization problem of current blockchain applications. We believe this work will be helpful for anyone working in Big Data and information systems related-fields.

The concept of smart cities has gained popularity due to technological advances in areas such as the Internet of Things (IoT) and Big Data Analytics (BDA). Location-based services have emerged in such smart environments to improve people’s quality of life and generate statistics for mutual benefit. In this work, a stylized presence detection concept is proposed which uses Bluetooth Low Energy (BLE) beacons placed in locations of interest. Users can detect the BLE beacon identification number (ID) with personal devices such as cell phones and connected watches and transmit it along with a unique and randomly generated user ID. Blockchain technology is used for a storage back-end. Our proposal is by no means exhaustive and is intended to advance the discussion of location-based services that deal with big data.

Many real-world complex systems can be modelled by temporal networks. Representation learning on these networks often captures their dynamic evolution and is a first step for performing further analysis, e.g. node classification. Node classification is a fundamental task for graph analysis in general and in the context of temporal graph, is often employed to categories nodes based on their activity patterns. Analysis of existing real world networks from different high-stake domains reveals that the rate of the malicious activities is on uptick, resulting in catastrophic social or economic consequences. This strongly motivates designing accurate node classification methods for temporal graphs. In this paper, we propose TGbase, for node classification on weighted temporal networks. TGbase efficiently extracts key features to consider the structural characteristics of each node and its neighborhood as well as the intensity and timestamp of the interactions among node pairs. These features accurately differentiate different classes of nodes, as shown on eight real-world benchmark datasets, outperforming multiple state-of-the-art (SOTA) deep/complex models. Our strong yet simple model is also generic, whereas the SOTA contenders are designed often for their specific (class of) datasets.

Blockchain technology is enabled by consensus algorithms to manage the relationships among several economic or business operators without human intervention. With the help of consensus algorithms, distributed systems can reliably reach agreement even if part of the system is faulty. Blockchain yields many benefits, among others, traceability, transparency, and security. We consider using the RAFT consensus algorithm to achieve robust and scalable decentralized applications, with focus on healthcare. We propose a stylized healthcare network, enabled by RAFT and built upon Hyperledger Fabric to showcase the use of RAFT in healthcare blockchain. However, RAFT is by no means limited to healthcare record systems, and can be applied to any other record system and value chain. Our paper offers several insights to those working in value chains and information management-related fields. In addition, we end our study with some future research avenues that may inspire managers and scholars to build or refine new decentralized systems in healthcare and other related fields.

Heterogeneous multi-core processing is increasingly adopted in embedded systems. Heterogeneous platforms can provide energy consumption reduction by employing longstanding techniques like Dynamic Voltage and Frequency Scaling (DVFS) and Dynamic Power Management (DPM). An effective energy-management strategy simultaneously exploits hardware-and software-level energy-reduction techniques. Energy-efficient partitioning is one software-level method where task allocation to heterogeneous clusters directly impacts the total system energy. In this paper, we couple the problem of energy-efficient partitioning on single-ISA heterogeneous platforms with task-aware scheduling. Tasks differ in their instruction mix, cache, memory and I/O access, execution path, and active processing and SoC circuitry. This affects their power demand. We make further use of underlying hardware frequency scaling to reduce the system energy. We propose four variants of our Task and Cluster Heterogeneity Aware Partitioning (TCHAP) targeting ARM big.LITTLE platforms, and show that our algorithms achieve up to 30 percent energy-reduction on average compared to a state-of-the-art scheme.

We propose a convolutional neural network (CNN) architecture for image classification based on subband decomposition of the image using wavelets. The proposed architecture decomposes the input image spectra into multiple critically sampled subbands, extracts features using a single CNN per sub-band, and finally, performs classification by combining the extracted features using a fully connected layer. Processing each of the subbands by an individual CNN, thereby limiting the learning scope of each CNN to a single subband, imposes a form of structural regularization. This provides better generalization capability as seen by the presented results. The proposed architecture achieves best-in-class performance in terms of total multiply-add-accumulator operations and nearly best-in-class performance in terms of total parameters required, yet it maintains competitive classification performance. We also show the proposed architecture is more robust than the regular full-band CNN to noise caused by weight-and-bias quantization and input quantization.

The increasing demand for wireless data transmission between wearable health care devices and central processing equipment has caused a consequential growth in the need for effective and reliable wireless body area network solution. The latest international standard, IEEE 802.15.6-2012 specifies the characteristics of the physical layer (PHY), multiple access control (MAC) layer, and security scheme. However, the system-level testbed gradually becomes a great challenge for the development of WBAN systems compared with other prevailing communication protocols such as Bluetooth and Zigbee. In this paper, we introduce a Software Defined Radio(SDR) based Testbed for WBAN. Benefiting from the rapid prototyping nature of the SDR platform, this testbed is shown to provide a solid testing environment for WBAN developers, as well as good testbed candidate for the future updated protocols.

Prolonged monitoring of breathing under different physical conditions is important in many applications for personal health tracking or in hospitals. Ultrasound technology has been used widely for imaging and diagnosis of the human body. In this work, we introduce the use of ultrasound for human respiratory monitoring. The proposed system measures the respiration rate by capturing ultrasound reflections from heart and surrounding organ motions due to the breathing. This system is based on ultrasound B-mode to measure the Time Of Flight (TOF), amplitude and phase of reflected ultrasound signals generated by piezo sensors working at 1 MHz. Experimental results show that the system can obtain respiratory signal with an accuracy of 89% as compared to a SPR-BTA spirometer. A prototype is designed with low complexity hardware, delivering 89% accuracy of the obtained respiratory signal in comparison to a SPR-BTA spirometer.

Body Area Networks (BAN) have caused wide interest in academic and industrial areas in recent years due to the strong demands of health condition monitoring by people. Consequently, security becomes a critical consideration, which restricts the development of BAN while the data transferring in BAN is increasingly significant and their privacy is of the utmost importance. Therefore, an ASIC implementation of security scheme for BAN is proposed by the authors, based on the IEEE standard 802.15.6, which is synthesized using the SIMC 65nm CMOS technology.

Body area networks (BANs) are systems of wearable computing devices for long‐term monitoring of personal health care. BAN is an emerging technology for the worldwide ageing population. In the BAN system, the transceiver is the most energy‐consuming part of a sensor node and radio transmission in the vicinity of the human body is highly lossy and inefficient. Therefore, the energy of the sensor node constraints the life cycle and quality of service of the network; consequently, low‐cost protocol shaves attracted wide interest. This study proposes a frame structure model of a self‐adaptive guard band protocol, which introduces a GB in each time slot according to the allowed maximum time drift of the crystal, adaptively adjusts the value of the GB based on the actual time drift, and then ensures that the node simultaneously maintains the sleeping state and synchronisation with the coordinator during beacon transmission, thus reducing the energy consumption.

In this paper, we validate a novel wearable device for real time non-invasive hydration monitoring. An experiment was carried out on three sets of 12 subjects under various exercise intensities to identify how the received signal strength indicator (RSSI) captured with the device relates to the change in the body hydration, body water loss percentage (BWL%). A linear regression correlation R2of 0.77 and a third degree polynomials correlation (R2=0.83) between ΔRSSI and BWL% is established based on the observation of the experiment, which implies that the hydration status can be quantized as body water loss by measuring ΔRSSI. Therefore, the technique and device is verified to be a potentially solid solution for wearable non-invasive real-time hydration monitoring device.

Noninvasive wearable human health monitoring devices are developed to improve the comfort, convenience, and security of humans in their life. Ultrasound technology has been used for imaging the human body for over half a century. In this study, the use of ultrasound as a wearable device for human health monitoring is introduced. This work investigates analysis of the heart motions for heart rate extraction. Experimental results showed promising performance of the proposed method in reference to an electrocardiogram device. A low power and low complexity hardware prototype is designed to measure the Time Of Flight (TOF) and amplitude of reflected ultrasound signals generated by piezo sensors at 1 MHz (nominally), under design considerations for safety issues of intensity exposure defined by FDA. This type of a wearable human-interactive device represents a promising platform not only for heart rate measurement but also for more feasible features such as respiration rate. A new technique is applied to minimize the signal processing time and ensure the device response correctness.

This paper presents a low-complexity compression scheme of electrocardiogram (ECG) signals based on the Haar wavelet transform (HWT) for use on mobile devices. An experimental, wearable, multi-lead ECG monitor was also developed and served as a testing platform for the proposed compression scheme. The proposed scheme was applied to all 48 recordings of the MIT-BIH arrhythmia database, where a percent root mean square difference (PRD) of 3.11 along with a compression ratio (CR) of 21.38:1 was achieved on average. The proposed scheme was also tested using raw multi-lead captures from the experimental device where an average PRD and CR of 9.77 and 24.95:1 was achieved respectively. The proposed HWT based compression scheme was efficiently implemented on a mobile platform and is capable of compressing multi-lead ECG signals, allowing for efficient data management in the context of data storage or data transmission.

Atomistic-based approaches accurately model Bias Temperature Instability phenomena, but they suffer from prolonged execution times, preventing their seamless integration in system-level analysis flows. In this paper we present a comprehensive flow that combines the accuracy of Capture Emission Time (CET) maps with the efficiency of the Compact Digital Waveform (CDW) representation. That way, we capture the true workload-dependent BTI-induced degradation of selected CPU components. First, we show that existing works that assume constant stress patterns fail to account for workload dependency leading to fundamental estimation errors. Second, we evaluate the impact of different real workloads on selected CPU sub-blocks from a commercial processor design. To the best of our knowledge, this is the first work that combines atomistic property and true workload-dependency for variability analysis.

Respiratory disorder is a highly prevalent condition associated with many adverse health problems. As the current means of diagnosis are obtrusive and ill-suited for real-time m-health applications, we explore a convenient and low-cost automatic approach that uses wearable microelectromechanical system sensor technology. The proposed system introduces the use of motion sensors to detect the changes in the anterior-posterior diameter of the chest wall during breathing function as well as extracting the informative respiratory features to be used for breathing disorders classification. Extensive evaluations are provided on six well-known classifiers with novel feature extraction techniques to distinguish among eight different pathological breathing patterns. The effects of the number of sensors, sensor placement, as well as feature selection on the classification performance are discussed. The experimental results conducted with ten subjects show the best accuracy rates of 97.50% by support vector machine and 97.37% with decision tree bagging (DTB) with all features and after feature selection, correspondingly. Furthermore, a binary classification is proposed for distinguishing between healthy people and patients with breath problems. The different assessments of classification parameters are provided by measuring the accuracy, sensitivity, specificity, F1-score and Mathew correlation coefficient. The accuracy rates above 98% suggest superior performance of DTB in binary recognition supported by the suggested new features.

Non-volatile storage is an important element for many low-power wearable sensor platforms for data aggregation, audit logs, and to enable offline analytics and debugging. NAND flash is an increasingly appealing choice due to its low cost, low power consumption, and small footprint; but it requires high software complexity and overhead to use effectively in such resource-constrained environments. Many wearable processing systems have limited program memory and RAM, on the order of kilobytes, however current NAND flash file systems require 10s of kilobytes of code and RAM to provide rudimentary logging facilities to SD cards or flash memories. By constraining access patterns to practical cases for logging and optimizing operations around the timing needs of real-time systems, we can do better. This paper presents the design and evaluation of a NAND flash logging file system, available freely under a permissive license, in only a few kilobytes of ROM and a few hundred bytes of RAM.

In this paper, we propose EDA methodologies for efficient, datapath-wide reliability analysis under Bias Temperature Instability (BTI). The proposed EDA flow combines the efficiency of atomistic, pseudo-transient BTI modeling with the accuracy of commercial Static Timing Analysis (STA) tools. In order to reduce the transistor inventory that needs to be tracked by the STA solver, we develop a threshold-pruning methodology to identify the variation-critical part of a design. That way, we accelerate variation-aware STA iterations, with a maximum speedup of 6.82x achieved for representative benchmark circuits. We substantiate the efficiency of the proposed framework for realistic designs. For a CPU datapath, our threshold-pruning technique outperforms built-in pruning commands of the STA solver by 16.87% in terms of runtime improvement. We demonstrate the impact of BTI after three years of operation, with clock frequency degradation up to 24% and functional yield reduction below 90% for higher frequencies.

In recent years, on-chip trace generation has been recognized as a solution to the debugging of increasingly complex software. An execution trace can be seen as the most fundamentally useful type of trace, allowing the execution path of software to be determined post hoc. However, the bandwidth required to output such a trace can be excessive. Our architecture-aware trace compression (AATC) scheme adds an on-chip branch predictor and branch target buffer to reduce the volume of execution trace data in real time through on-chip compression. Novel redundancy reduction strategies are employed, most notably in exploiting the widespread use of linked branches and the compiler-driven movement of return addresses between link register, stack, and program counter. In doing so, the volume of branch target addresses is reduced by 52%, whereas other algorithmic improvements further decrease trace volume. An analysis of spatial and temporal redundancy in the trace stream allows a comparison of encoding strategies to be made for systematically increasing compression performance. A combination of differential, Fibonacci, VarLen, and Move-to-Front encodings are chosen to produce two compressor variants: a performance-focused xAATC that encodes 56.5 instructions/bit using 24,133 gates and an area-efficient fAATC that encodes 48.1 instructions/bit using only 9,854 gates.

A reliable long-term monitoring and diagnosis of breath disorders at an early stage provides an improvement of medical act, life expectancy, and quality of life while decreasing the costs of treatment and medical services. Therefore, a real-time unobtrusive monitoring of respiration patterns, as well as breath parameters, is a critical need in medical applications. In this paper, we propose an intelligent system for patient home care, capable of measuring respiration rate and tidal volume variability via a wearable sensing technology. The proposed system is designed particularly for the goal of diagnosis and treatment in patients with pathological breathing, e.g., respiratory complications after surgery or sleep disorders. The complete system was comprised of wearable calibrated accelerometer sensor, Bluetooth low energy, and cloud database. The experiments are conducted with eight subjects and the overall error in respiration rate calculation is obtained 0.29%±0.33% considering SPR-BTA spirometer as the reference. We also introduce a method for tidal volume variability estimation while validated using Pearson correlation. Furthermore, since it is essential to detect the critical events resulted from sudden rise or fall in per breath tidal volume of the patients, we provide a technique to automatically find the accurate threshold values based on each individual breath characteristics. Therefore, the system is able to detect the major changes, precisely by more than 98%, and provide immediate feedback such as sound alarm for round-the-clock respiration monitoring.

Automated methods of real-time and un-obstructive patient's respiration and position monitoring have been subjects of interests in e-health applications. The present study implements a low-cost and convenient monitoring system for patients with breathing problems or sleep disorders. We have also captured the Rib Cage (RC) and Abdomen (AB) movements using accelerometer sensors. In addition to measurement of phase shift between the chest wall compartments, the impacts of different body positions on AB and RC motions have been investigated. The performance of the presented system is evaluated and the average Mean Square Error (MSE) of 0.14 is achieved for three breath timing variables. Moreover, the overall errors of phase angles for paradoxical and synchronous breath patterns are 0.25°±0.06 and 0.26°±6E-03, respectively. The system properly indicates a significant increase in the degree of ribcage and abdomen asynchrony in the paradoxical breathing compared to normal pattern.

The main goal of post-silicon debugging is to locate errors undetected during the pre-silicon verification. Although high speed of hardware prototype can be leveraged to expedite running a large number of realistic test vectors, the low level of observability and controllability of signals inside a prototype is a big concern. Design for Debug (DFD) techniques aim to improve the observability of signals and speed up the root-cause analysis of errors. Incorporation of an Embedded Logic Analyzer (ELA) is introduced as one of the practical DFD techniques. An ELA contains a trigger unit that controls conditions for which trace signals should be captured in a buffer for post-processing. In this paper, we propose a tool to generate hierarchical triggers, providing compact trace information for root-cause analysis. Major advantages of our technique as a means to generate trigger units are: 1) failure localization and root-cause analysis is expedited by keeping the hierarchical trace of interactions leading to failures, 2) overlapped failure patterns can be found by mechanism which results in a 60-65% reduction in hardware overhead compared to the previously proposed method, 3) it can be parameterized to generate several units, making it possible to incorporate checkers into scarce silicon area and enabling on-chip debugging by means of time-multiplexing scheme.

In software debugging, trace generation techniques are used to resolve highly complex bugs. However, the emulators increasingly used for embedded software development do not yet offer the types of trace generation infrastructure available in hardware. In this article, we make changes to the ARM ISA emulation of the QEMU emulator to allow for continuous instruction-level trace generation. Using a standard GDB client, tracepoints can be inserted to dynamically log registers and memory addresses without altering executing code. The ability to run trace experiments in five different modes allows the scope of trace generation to be narrowed as needed, down to the level of a single Linux process. Our scheme collects the execution traces of a Linux process on average between 9.6x--0.7x the speed of existing QEMU trace capabilities, with 96.7% less trace data volume. Compared to a software-instrumented tracing scheme, our method is both unobtrusive and performs on average between 3--4 orders of magnitude faster.

Accelerometers are vital parts of many industrial and biomedical applications. Such applications have high demands for accuracy. Multi-sensor fusion is an efficient approach to deliver accurate sensor readouts that are tolerant to multiple faults. This paper proposes an efficient data fusion algorithm, which minimizes Mean-Square-Error (MSE) and keeps the overall precision of the system high. We make use of a convex optimization scheme to tackle the problem. Furthermore, a pre-processing step called screening is used to exclude the potentially faulty sensors from the data fusion. The screening process makes it possible to quickly detect multiple faulty sensors. Our data fusion approach is applicable to any multi-sensor system, for which the post-calibration statistical characteristics of sensors can be measured experimentally. However, the results are presented for accelerometers.

Modern embedded systems require design methodologies that are productive, yet manage to harvest continuing innovations in embedded processor and sensing technologies. This course outlines techniques for mastering the design using the new tools and software abstractions based on ARM Cortex M processor family. Methodologies are outlined that enhance productivity in large-scale designs, while also employing the advanced hardware accelerators present in modern embedded processors. We then elaborate the ways to design and use platforms for networked systems that build on multi-sensor integration functions.

The synchronization of accesses to shared memory buffers in multi-core platforms can be realized through lock-based synchronization protocols. If the embedded application executing on the system has hard real-time constraints, the worst-case blocking times for accessing remotely shared resources can negatively impact the schedulability guarantee. In this case, wait-free communication protocols can be an effective alternative. In addition, in a model-based development process, wait-free buffers allow the realization of communication that provably preserves the signal flows and guarantees a correct implementation. Flow-preserving wait-free communication primitives require (in the general case) the execution of buffer updates procedures at task activation time, either by the kernel or by a hook procedure executing at the highest priority level. To minimize the interference of such procedures on the application-level tasks, we present and evaluate an FPGA implementation. Our FPGA implementation is compared with implementations of lock-based policies in terms of memory, time, and area overhead.

Assertions are now widely used in verification as a means to help convey designer intent and also to simplify the detection of erroneous conditions by the firing of assertions. With this expressive modeling power, assertions could also be used for tasks such as helping to assess test coverage and even as a source for test generation. Our work deals with this last aspect, namely, assertion-based test generation. In this article, we present our compacted test generation scheme based on assertions. Novel compaction techniques are presented based on assertion clustering, test-path overlap detection and parallel-path removal. Our compaction approach is experimentally evaluated using nearly 300 assertions to show the amount of reduction that can be obtained in the size of the test sets. This ultimately has a positive impact on verification time in the quest for bugfree designs.

Multi-sensor data fusion is an efficient method to provide both accurate and fault-tolerant sensor readouts. Furthermore, detection of faults in a reasonably short amount of time is crucial for applications dealing with high risks. In order to deliver high accuracies for the sensor measurements, it is required to perform a calibration for each sensor. This paper focuses on designing a fault-tolerant calibrated multisensor system. First, the least squares method is applied to calibrate each sensor using a linear curve fitting function. Next, an analytical technique is proposed to carry out a fault-tolerant multi-sensor data fusion, while minimizing the Mean-Square-Error (MSE) for the final sensor readout. While our data fusion approach is applicable to different multi-sensor systems, the experimental results are shown for 16 temperature sensors, where an environmental thermal chamber was used as the reference model to calibrate the sensors and perform the measurements.

Analyses of range and precision are important for high-level synthesis and verification of fixed-point circuits. Conventional range and precision analysis methods mostly focus on combinational arithmetic circuits and suffer from major inefficiencies when dealing with sequential linear-time-invariant circuits. Such problems mainly include inability to analyze precision when quantization of constant coefficients is taken into account, and lacking efficient word-length optimization algorithms to handle both variables and constants, while satisfying the error metrics. The algorithms presented in this paper solve these problems. Experiments illustrate the efficiency and robustness of our algorithms.

We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source.

Range analysis is an important task in obtaining the correct, yet fast and inexpensive arithmetic circuits. The traditional methods, either simulation-based or static, have the disadvantage of low efficiency and coarse bounds, which may lead to unnecessary bits. In this paper, we propose a new method that combines several techniques to perform fixed-point range analysis in a datapath towards obtaining the much tighter ranges efficiently. We show that the range and the bit-width allocation can be obtained with better results relative to the past methods, and in significantly shorter time.

Statistical data from many application fields confirm that SoC products implemented in modern deep submicron technologies are getting more and more susceptible to transient errors. Although thorough and comprehensive understanding of the services that SoCs provide is the key to systematic development, designers no longer can ignore the emerging reliability issues. In fact, proper actions should be carried out at various stage of production to mitigate the effect of transient errors. Having failure rate of a system at early stage of SoC development will help companies and designers to make right decisions at right time concerning the usage of error protection mechanisms with suitable intensity across different modules. This paper proposes a new method to estimate failure rate of modules inside a SoC.

In the multicore era, capturing execution traces of processors is indispensable to debugging complex software. The inability to transfer vast amounts of trace data off-chip without significant slow-down has impeded the debugging of such software, in both pre-silicon emulation and in real designs. We consider on-chip trace compression performed in hardware to reduce data volume, using techniques that exploit inherent higher-order redundancy in address trace data. While hardware trace compression is often restricted to poor or moderate performance due to area and memory constraints, we present a parameterizable scheme that leverages the resources already found on existing platforms. Harnessing resources such as existing trace buffers on CPUs, and unused embedded memory on FPGA emulation platforms, our trace compression scheme requires only a small additional hardware area to achieve superior compression ratios.

With a significant increase in the design complexity of cores and associated communication among them, post-silicon validation has become a demanding task in System on Chips (SoCs) design. To ensure that final products are fault-free and ready for market, the post-silicon validation goal is to catch bugs and pinpoint the root causes of errors that could escape from pre-silicon verification tools. Post-silicon validation involves running a hardware prototype in an environment that is similar to its final platform with its expected workload. As new SoCs tend to have many cores, the interactions among these cores are becoming so complex that post-silicon debug techniques should address not only validation of the functional aspects of a design but such techniques have to “bulletproof” the communication and synchronization among cores inside an SoC. In this paper, we propose an AXI based environment for post-silicon validation. The proposed environment involves Local Debugging Unit (LDU) and Shared Debugging Unit (SDU). LDU monitors trace of transactions issued by the hardware prototype and detect undesired conditions on bus. SDU combines debug traces from different LDUs. We embed the proposed SDU inside an AXI configurable interconnect. Major benefits of using our proposed debug platform over traditional techniques for silicon validation are as follows: 1) it detects and bypasses real time severe faulty conditions such as deadlocks resulting from design errors or electrical faults 2) there is no need for internal trace memory because SDU can communicate to the external memory through slave ports 3) it enables online monitoring of the trace buffer.

Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon debugging based on the insertion of hardware checkers in the debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardware-assertions and controlling each cluster selectively during the debug mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient debug scheduling.

Modern assertion languages such as property specification language (PSL) and SystemVerilog assertions include many language constructs. By far, the most economical way to process the full languages in automated tools is to rewrite the majority of operators to a small set of base cases, which are then processed in an efficient way. Since recent rewrite attempts in the literature have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, ensuring that the rewrite rules are correct is a major contribution toward ensuring that the tools are correct, and even that the semantics of the assertion languages are well founded. This paper outlines the methodology for computer-assisted proofs of several publicly known rewrite rules for PSL properties. We first present the ways to express the PSL syntax and semantics in the prototype verification system (PVS) theorem prover, and then prove or disprove the correctness of over 50 rewrite rules published without proofs in various sources in the literature. In doing so, we also demonstrate how to circumvent known issues with PSL semantics regarding the${\ssr never}$and${\ssr eventually}!$operators, and offer our proposals on assertion language semantics.

Arithmetic circuits in general do not match specifications exactly, leading to different implementations within allowed imprecision. We present a technique to search for the least expensive fixed-point implementations for a given error bound. The method is practical in real applications and overcomes traditional precision analysis pessimism, as it allows simultaneous selection of multiple word lengths and even some function approximation, primarily based on Taylor series. Starting from real-valued representation, such as Taylor series, we rely on arithmetic transform to explore maximum imprecision by a branch-and-bound search algorithm to investigate imprecision. We also adopt a new tight-bound interval scheme, and derive a precision optimization algorithm that explores multiple precision parameters to get an implementation with smallest area cost.

We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular standard cell approach that compensates intra-die temperature and process variances. Our clock distribution provides control over regional clock skew, permits use in beneficial skew applications and facilitates silicon-debug. By adding routing to the serial clock network, we permit post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability to the network.

To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels. In particular, in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports. Moreover, our proposed RAVC router isolates the faulty router from occupying network bandwidth. Experimental result shows that proposed micro-architecture provides 7.1% and 3.1 % average latency decrease under uniform and transpose traffic pattern. Considering the existence of failures in routers of on-chip network, RAVC provides 28% and 16% decrease in the average packet latency under the uniform and transpose traffic pattern respectively.

To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monitors and generators, we have extended the monitor generator tool MYGEN to produce synthesizable on-line generators. We have tested the resulting generators in simulation and by emulation on an FPGA. The combination of multiple generators provides an efficient way to model the environment of modules within a DUT, facilitating an equivalent of software "unit testing" under real conditions, early in the design flow.

We present a low-cost on-line system for clock skew management in integrated circuits. Our built-in clock skew system (BICSS) uses a centralized approach to identify, quantify and correct skew using a two-step method. The technique assesses the time-off-light between the central debug circuitry and each region, or tap under test to account for the measurement error due to differences in path length common in existing techniques. The system can be used to detect skew above a user-adjustable margin using a variable tolerance phase detector. The result is a solution which provides silicon debug and repair capability of on-chip clock skews with a very small area overhead.

Assertion-based verification with languages such as PSL is gaining in importance. From assertions, one can generate hardware assertion checkers for use in emulation, simulation acceleration and silicon debug. We present techniques for checker generation of the complete set of PSL properties , including all variants of operators, both strong and weak. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations that can not be done in a modular approach where subcircuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is derived for other operators. Automata splitting is introduced for an efficient implementation of the eventually! operator.

The mesh network-on-chip (NoC) topology has its drawbacks in the communication latency scalability, and the concentration of the traffic in the center of the mesh. We propose a topology where a traditional wormhole-routed mesh network is augmented by a hierarchical ring interconnect for routing global traffic. In addition to the topology, the routing strategies have a large impact on system performance. We compare the performance of a deterministic and adaptive routing strategy when applied to our augmented topology. A SystemC modeling platform was used to compare the traditional wormhole–routed mesh with the augmented architecture. The proposed architecture reduces the average latencies incurred by global traffic, while the application of a adaptive routing strategy can further increase performance.

In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used assertion-based verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.

Phase-Locked Loops (PLLs) are versatile modules for synchronization and applications such as high-speed serial interfaces in System-on-Chips (SoCs). Their precisions are critical to proper functioning of the SoCs. Intermodule interference such as simultaneous switching noise (SSN) is time-varying, where the stationary assumption in conventional jitter analysis does not apply. We propose a methodology to compute PLL jitter by investigating the harmonic relations between the PLL system with SSN. This provides statistical analysis over many VCO design parameters, SoC modules and noise barrier configurations. Its accuracy and efficiency are compared against circuit simulations.

This paper considers the synthesis of reversible circuits directly from an irreversible specification, with no need for producing a reversible embedding first. The authors present a feasible methodology for realizing the networks of reversible gates, in a manner that builds on the classical technology mapping. We do not restrict ourselves to the restricted notion of realizing permutation functions, and construct reversible implementations where extraneous signals are efficiently reused for overcoming the inherent fanout limitation

In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interference in mixed-signal environments cause designers to be less reliant on optimization based solely on schematic models. Performance can be further improved at the physical design level. Hierarchical optimization schemes are used to manage the complexity in the analog circuit design process. In this paper, we present a novel performance-driven compaction optimization algorithm that optimizes the placement of circuit blocks and guard bands for analog circuits. Parasitic effects are minimized under symmetry, matching and displacement constraints derived from the customized layout topology.

We present the circuitry required for implementing a multi-clock reconfigurable, reprogrammable clock distribution network for integrated circuits using a reference-based scheme for skew compensation. In the scheme, a device is subdivided into multiple regions and a bi-directional clock distribution line is daisy-chained through the device, connecting each region in the domain. Switching structures that can be used to re-route the clock chain are added where needed. The proposed design simplifies layout for irregularly shaped clock domains and provides flexibility to designers by enabling post-fabrication changes to the clock distribution network. Reconfigurable clock distribution networks can be used in some ASICs, SoCs and FPGAs. The reference-based approach used is applicable to both single and multiple clock distributions

Jitter test in production is notorious for its long test time and the challenge of accuracy verification. Among various types of jitter, Random Jitter (RJ) is most challenging to test on Automatic Test Equipment (ATE) because of its randomness. To be considered as a favorable jitter test in production for multi-gigabit devices, the RJ needs to be measured with sub-picosecond accuracy and the whole test time is expected to be in a few tens of milliseconds. However, no known solutions meet these criteria to our best knowledge. In this paper, we present a systematic solution for multiple Giga-bit-per-second (Gbps) Transmitter (TX) jitter testing on ATE. Our undersampling-based solution extracts jitter either from edge histograms in time domain or from the jitter spectrum in frequency domain. Both approaches provide a RJ precision better than ±0.5ps and are capable of finishing the whole TX test within 100ms. We have verified the solution with data rates up to 6Gbps and applied it in mass production.

A popular network topology for network-on-chip (NoC) implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic. This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect. Hierarchical rings have been selected for study because of their simplicity, speed and efficiency in embedding onto a circuit layout, as well as for their suitability for efficient cache coherent protocols. An original SystemC modeling platform was implemented in order to compare the traditional 2D-mesh with the hybrid ring architectures and the simulation results will show that our hybrid architecture does indeed have a positive effect on the average hop count

Quantum Fourier transform (QFT) plays a principal role in the development of efficient quantum algorithms. Since the number of quantum bits that can be built is limited, while many quantum technologies are inherently three (or more) valued, we consider extending the reach of the realistic quantum systems by building a QFT over ternary quantum digits. Compared to traditional binary QFT, the q-valued transform improves approximation properties and increases the state space by a factor of (q/2)n. Further, we use nonbinary QFT derivation to generalize and improve the approximation bounds for QFT

This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers, as well as the improved metrics relating to the coverage of assertion checkers. The proposed techniques have been successfully incorporated into the MBAC checker generator.

In our previous publication (Cai, et. al., 2005), we demonstrated the ability to generate the proper mix of jitter on ATE to enable the jitter tolerance test for 1.5/3Gbps SATA applications. Obviously this is not the only challenge for performing this test on ATE. Jitter tolerance compliance test for SerDes calls for validation of bit-error-rate (BER) down to the 10-12or lower. This requirement deemed this test to be extremely time-consuming, which normally takes more than an hour (assuming running 1013bits for 10-12BER level guaranteed). While in the ATE world every test is measured in seconds or even in milliseconds; it is obviously impractical to adopt this test directly. In this paper we demonstrate a new technique to perform the jitter tolerance test >1000 times faster. The technique of course involves extrapolation from the higher BER region down to the 10-12level for the compliance test, but the challenge that we faced in getting the extrapolation is very different from the conventional transmitter jitter measurement world. We present a new mathematical model suitable to reason about this extrapolation process

We consider self-testing of complete wireless nodes in the field through a low-energy software-based self-test (SBST) method. Energy consumption is optimized both for individual components such as a CPU, embedded memories, and an RF module, as well as at the system level, considering the interplay between module tests. We first derive a scheme for software-based tests with the least amount of cycles and with operands of least Hamming distance and weight. Time interleaving of module tests at the system level further reduces the overall test energy consumption

This paper addresses the issue of obtaining compact canonical representations of datapath circuits with sequential elements for the purpose of equivalence checking and component matching. First, the authors demonstrate the mechanisms for an efficient compositional construction of the arithmetic transform (AT), which is the underlying function representation used in modern word-level decision diagrams (WLDDs). Second, presented is a way of generating the canonical transforms of the sequential and imprecise datapath circuits

The need for mass-produced inexpensive wireless devices operating under strict energy constraints poses new challenges in the system design methodology. This paper presents a methodology for designing wireless nodes in which a low cost, reliable antenna is realized by printed circuit traces. We show how to combine the analysis from 2.5D and 3D EM simulators with the PCB design tools to create predictable nodes with printed antennas that meet stringent power and data transmission range goals. The presented approach is applied to the design of a IEEE802.15.4 wireless node deployed in several indoor environments.

Assertion-based verification (ABV) is emerging as a paramount technique for industrial-strength hardware verification, especially through the emerging property specification language (PSL). Since PSL introduces significant overhead to simulators, in this paper we present the infrastructure for hardware emulation capable of supporting ABV. We develop a tool that generates hardware assertion checkers for inclusion into efficient circuit emulation. The MBAC checker generator is outlined, together with the algorithms for optimized assertion-circuit generation. Experiments show that MBAC outperforms the best known checker-generator.

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.

Quantum computing offers immense speedup in performing tasks such as data encryption and searching. The quantum algorithms can be modeled using classical computing devices, however classical computer simulations cannot deal efficiently with the parallelism present in quantum algorithms. The quantum circuit model for quantum algorithms is sufficient to describe the known quantum algorithms. Using analogies between quantum and digital circuits, we design the emulator of quantum algorithms in FPGAs that allows efficient experimentation with new quantum algorithms. This paper concentrates on new techniques for modeling quantum circuits, including the entanglement and probabilistic computing realization, as well as the critical issues in the required precision of computing.

Wireless sensor networks (WSNs) are being increasingly used in applications where low energy consumption and low cost are the overriding considerations. With increased use, their reliability, availability and serviceability need to be addressed from the outset. Conventional schemes of adding redundant nodes and incorporating reliability in control protocols can effectively improve only the reliability of the overall WSN. The availability and serviceability of WSN nodes can be addressed by providing the remote testing and repair infrastructure for the individual sensor nodes that is well matched with existing on-board test infrastructure, including standard JTAG chains. We propose and evaluate scalable architectures of WSN nodes for increased availability as well as implement the proposed solutions using COTS components.

We investigate methodology for simulation-based verification under a fault model. Since it is currently not feasible to describe a comprehensive explicit model of design errors, we propose an implicit fault model. The model is based on the arithmetic transform (AT) spectral representation of faults. The verification of circuits under the small errors in spectral domain is then performed by the universal test set (UTS) approach to test vector generation. The major result shows that, for errors whose AT has at most t nonzero coefficients, there exist the UTS test vector set of size O(n/sub 2//sup log t/). Consequently, verification confidence can be parameterized by the size of the error t, where at most O(n/sub 2//sup log t/) verification vectors are simulated to verify the absence of faults belonging to such an implicitly defined fault class. The experimental confirmation of the feasibility of verification using such UTS is presented, together with the relations between the arithmetic and Walsh-Hadamard spectra that bound the AT error spectrum and show that a class of small error circuits has small error spectrum. The proposed approach has the advantage of compatibility with formal verification and testing methods.

FPGAs have witnessed an increased use of dedicated communication interfaces. With their increased use, it is becoming critical to test and properly characterize all such interfaces. Bit error rate (BER) characteristic is one of the basic measures of the performance of any digital communication system. We propose a scheme for BER testing in FPGAs, which exhibits a few orders of magnitude speedup compared to traditional software simulation methods. In this scheme, we include a novel implementation of an additive white Gaussian noise (AWGN) generator with high speed and high accuracy for channel emulator. Compared to traditional BER test products, our scheme can test BER under different noise conditions. The whole system is implemented as an IP core, suitable for a single FPGA device.

An architecture that combines a Globally Asynchronous, Locally Synchronous (GALS) [1,2] design style with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimum power consumption. The proposed Globally Asynchronous, Locally Dynamic System (GALDS) requires three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently-clocked synchronous blocks [3], an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally-controlled oscillator to generate global fixed frequency clocks required by the all-digital dynamic clock generator. These circuits have been designed and simulated for all the tasks required to implement a complete GALDS infrastructure. The architecture is easily scaled due to the modular nature of these circuits and is useful for a wide range of applications.

The layered system design approach has shown its strength in the design of the network and other complex systems. In this paper, we apply this approach to the design of system testing interfaces. The system is partitioned into layers to maximize reuse, and ease the development. In this paper, we demonstrate this methodology by designing a low-overhead testing interface and circuitry for the Infiniband Architecture (IBA).

As device densities increase, testing cost is becoming a larger portion of the overall FPGA manufacturing cost. We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.

We address verification of imprecise datapath circuits with sequential elements. Using Arithmetic Transform (AT) and its extensions, we verify the sequential datapath circuits with finite precision. An efficient formulation of the precision verification is presented as a polynomial maximization search over Boolean inputs. Using a branch-and-bound search for the precision error and the block-level composition of ATs, we verify the approximated, rounded and truncated pipelined datapaths.

We present a new multivariate interpolation algorithm over arbitrary fields which is primarily suited for small finite fields. Given function values at arbitrary t points, we show that it is possible to find an n-variable interpolating polynomial with at most t terms, using the number of field operations that is polynomial in t and n. The algorithm exploits the structure of the multivariate generalized Vandermonde matrix associated with the problem. Relative to the univariate interpolation, only the minimal degree selection of terms cannot be guaranteed and several term selection heuristics are investigated toward obtaining low-degree polynomials. The algorithms were applied to obtain Reed-Muller and related transforms for incompletely specified functions.

We address the issue of obtaining compact canonical representations of datapath circuits with sequential elements, for the purpose of equivalence checking. First, we demonstrate the mechanisms for efficient compositional construction of arithmetic transform (AT), which is the underlying function representation, used in modern word-level decision diagrams. Next, we introduce a way of generating the canonical transforms of the sequential datapath circuits. Using these principles, we verify by AT the highly sequential distributed arithmetic architectures.

This paper considers verification of combinational circuits by test vectors under assumption of gate and wire replacement faults. Identifying redundant faults is critical to the quality and speed of such verification schemes. We propose the first known exact redundancy identification of gate replacement faults, together with its efficient approximations. While both solutions use the SAT formulation of redundancy identification, we propose the means to effectively use any single stuck-at-value redundancy identification in the approximate schemes, with varying detection accuracy. Critical to the latter are the novel uses of don't care approximations that detect many redundant faults and quickly identify those that can be detected by methods for stuck-at value faults. A test generation scheme that uses the error-correcting properties of Arithmetic Transforms is incorporated into the overall verification procedure, and is shown to provide high fault coverage for these fault models.

No abstract available.

Small-scale multiprocessors are becoming increasingly economical and common, whereas larger multiprocessors continue to have higher per-node costs. The NUMAchine multiprocessor project seeks to make large-scale multiprocessors more economical while maintaining high performance by exploring architectural and hardware features for low-cost, modular multiprocessors. To demonstrate our approach, we have implemented a prototype system that is scalable to 128 processors. An efficient directory-based cache coherence protocol exploits our hierarchical ring-based interconnect and supports sequential consistency. This paper documents the design choices and the resulting performance of the system using both simulation results and measurements on the prototype hardware.

In this paper, we consider verification under error-model assumption. We exploit the algebraic properties of the arithmetic transforms that are used in compact graph-based representations of arithmetic circuits, such as *BMDs. Verification time can be shortened under the assumption of corrupting a bounded number of transform coefficients. Bounds are derived for a number of test vectors, and the vectors successfully verified arithmetic circuits under a class of error models derived from recently proposed basic design error classes, including single stuck-at faults.

In th,is paper, we consider a problem of interpolating a multivariate polynomial from its values at arbitrary t points ouf:r a field F. We derive a deterministic algorithm that finds an interpolating polynomial with at most t terms.Relative to the univariate inteq&otzon, minimal degree selection of terms and wxiqw:ness cannot be gualonteed.Our construction uses the nullspaces of th,e mlrltivnriate genwralized Vanderm.ondematrix associated ,with.the problem to make this mutrk nonsingulw in u series of stepas.Th.e strwtwe of this matrix ullows us to deterministicully find the terms thet increase the rank of this matrix.We pl'esent u pwctical algorithm for finite field interpolations, togeth,er with a set of heuristics for obtairhg fast CL small-de,gree interpolation polynomial.As a special case of interpolation a1gori.th.m. we propose the qlLadratic time algorithm for interpolation over GF(2) field.

This paper describes the design and implementation of the NUMAchine multiprocessor. As the market for CC-NUMA multiprocessors expands, this research project provides a timely architectural design and cost-effective prototype. The key to the successful implementation of our 48-processor prototype is the use of off-the-shelf components and programmable logic devices. Since this machine will serve as a research vehicle for parallel software development, a number of hardware features to enhance experimentation have been included in the design.

Many modern field programmable logic arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs such blocks, known as Universal Logic Modules (ULMs), have already been considered for application in FPGAs; we propose a new class of ULMs which is more useful in the FPGA environment. Methodology for systematic development of such blocks is presented, based on the BDD description of logic functions. We give an explicit construction of a three-input LUT replacement that requires only five programming bits, which is the optimum for such ULMs. A realistic size four-input LUT replacement is obtained which uses 13 programming bits.

This paper provides a case study that shows how a demanding application stresses the capabilities of today's CAD tools, especially in the integration of products from multiple vendors.We relate our experiences in the design of a large, high-speed multiprocessor computer, using state of the art CAD tools.All logic circuitry is targeted to field-programmable devices (FPDs).This choice amplifies the difficulties associated with achieving a highspeed design, and places extra requirements on the CAD tools.Two main CAD systems are discussed in the paper: Cadence Logic Workbench (LWB) is employed for board-level design, and Altera MAX+plusII is used for implementation of logic circuits in FPDs.Each of these products is of great value for our project, but the integration of the two is less than satisfactory.The paper describes a custom procedure that we developed for integrating sub-designs realized in FPDs (via MAX+plusII) into our board-level designs in LWB.We also discuss experiences with Logic Modelling Smart Models, for simulation of FPDs and other types of chips.

No abstract available.

This paper considers the Reed-Muller transform for incompletely specified multiple-valued logic functions, which is obtained as the finite field polynomial representation. A new algorithm for dealing with single-variable functions is presented. It is applicable to finite fields of small sizes (two to four), which is of interest because only these fields are readily implementable with today's MVL technology. It is shown how such or any similar single-variable algorithm can be used to obtain a fast n-variable Reed-Muller transform based on this transform, a heuristic scheme is derived for dealing with incompletely specified functions. It has better computational properties than other methods and achieves the best results when applied to functions with a large number of unspecified points.>