The SIMD (single instruction, multiple data) control style achieves a very cost effective processor element (PE) control mechanism. In this paper, two efficient data transfer operations for a SIMD PE array processor are proposed to address the inefficiency of most SIMD processor arrays in performing irregular memory access per PE. First, the SIMD random access provides simultaneous data transfer of randomly, from each PE independently addressed elements. Second, the SIMD ROI (region of interest) access enables concurrent data transfer of ROI areas with optional different ROI parameters for each PE. Speed-up values for both new transfer operations show an at least six times faster execution and the synthesis output reports an area increase of merely 1% for a 32 PE SIMD array processor configuration.

A scalable SIMD/MIMD mixed-mode parallel processor architecture called XC core is proposed to meet the high and diverse performance requirements of embedded multimedia applications. XC core supports both the SIMD and MIMD computing models at low hardware cost by dynamically reconfiguring itself into datapath circuits or control circuits, i.e., trading off between performance and flexibility. A control processor is used to broadcast instructions to a whole SIMD PE (Processing Element) array or to a part of it while assigning a separate program to each PU (Processing Unit), that is mainly composed of the hardware resources of several PEs. RTL synthesis results show that area overhead for reconfiguration is merely 10% of the total area. Benchmark results show that the SIMD mode is effectively achieving high performance towards the regular and massive data parallelism portions of applications, while the MIMD mode enables acceleration of the remaining part of applications whose implementation using a pure highly parallel SIMD architecture would otherwise be impossible. The results show that the XC core design is competitive against more complex processors, with respect to both its cost efficiency as a highly parallel SIMD processor and its flexibility as a multicore MIMD processor, against a wide range of applications.

This paper presents a Multi-DSP system for real- time SAR-processing using the HiPAR-DSP 16. We developed this full programmable processor at the Laboratorium f ¨ ur Informationstechnologie. With 16 parallel data paths and a two- dimensional memory it is optimized for image processing algo- rithms like FFT-transforms. SAR image synthesis methods, like the investigated ωk-algorithm, use the computational intensive FFT-transform. To overcome the large processing power of future realtime SAR image synthesis applications, several DSPs have to work in parallel. The presentedcompact SAR system can be easily adapted to match the demands of different SAR algorithms by scaling the number of processing nodes. Equiped with 6 HiPAR-DSP 16 a 233x175x15 mm 3 boardprovid es a realtime capability of processing SAR applications with a PRF of 1200 Hz. A rangeline length of 4096 8 bit complex samples and 4096 rangelines is assumed. The small volume and it's power consumption of less than 35 W enables it for on-boardusage in compact air- or spaceborne systems.

The presented HiPAR-DSP is a highly parallel DSP core for system on a chip video- and image processing applications. The architecture is based on an array of up to 16 parallel data paths steered by a single RISC controller in SIMD style. Each data path consists of three VLIW controlled arithmetical units: a 16 bit MAC and 32 bit ALU and shift & round units. A divided memory concept serves local caches for each data path as well as a special shared matrix memory which enables concurrent access from all data paths in every clock cycle. External connection can be provided via a modular DMA controller which enables an easy interfacing to other on chip modules. The HiPAR-DSP core has been manufactured in the most powerful version with 16 data paths in second Quarter 2001 and delivers with a maximum clock frequency of 100 MHz 4.8 GOPS peak and about 3 GOPS sustained performance. In addition to the core architecture the paper will also present the software development system for the HiPAR-DSP including C/C++ compiler, assembler, simulator and a PCI board with onboard video I/O interfaces.

At the University of Hannover a fully programmable DSP, the HiPAR-DSP 16, was developed. This HiPAR-DSP 16 contains 16 parallel datapaths and a 2-dimensional memory adapted to image processing algorithms. For real time SAR processing high computational power is required. Therefore a multi DSP board with 6 HiPAR-DSP 16 is developed. The high performance of up to 28 GOPS enables a SAR processing in real time. The calculation time for the wk-algorithm running on this board was estimated. For blocks of 4096 lines with 4096 8 bit complex samples real time processing is possible to a pulse repetition frequency (PRF) of 1200 Hz. Due to a low power consumption and the small size of 160/spl times/230 mm/sup 2/ of this board the use in on-board systems is predestinated.

Architecture and design of the HiPAR-DSP, a SIMD controlled signalprocessor with parallel data paths, VLIW and novel memory design.The processor architecture is derived from an analysis of thetarget algorithms and specified in VHDL on register transfer level.A team of more than 20 graduate students covered the whole designprocess, including the synthesizable VHDL description, synthesis,routing and backannotation as the development of a complete softwaredevelopment environment.The 175mm{2}, 0.5µm 3LM CMOSdesign with 1.2 million transistors operates at 80 MHz and achievesa sustained performance of more than 600 million arithmetic operations.

This paper presents a low-power, 32-bit RISC microprocessor with a 64-bit "single-instruction multiple-data" multimedia coprocessor, V830R/AV, and its MPEG-2 video decoding performance. This coprocessor basically performs multimedia-oriented four 16-bit operations every clock, such as multiply-accumulate with symmetric rounding and saturation, and accelerates computationally intensive procedures of the video decoding; an 8/spl times/8 IDCT is performed in 201 clocks. The processor employs the Concurrent Rambus DRAM interface, and facilities for controlling cache behavior explicitly by software to speed up enormous memory accesses necessary for motion compensation. The 200-MHz V830R/AV processor with the 600-Mbyte/s Concurrent Rambus DRAMs decodes MPEG-2 MP@ML video in real-time (30 frames/s).