The image understanding architecture (IUA) system is designed specifically for computer vision processing that relies heavily on artificial intelligence techniques to classify objects. To provide for low-, intermediate-, and high-level computer vision processing, the IUA system combines three heterogeneous levels of parallelism with associative processing mechanisms. The lowest level of the IUA contains a SIMD array of per pixel bit-serial processing elements with networking capabilities that exceed those of present bit-serial machines. The SIMD level is closely mated with a middle-level MIMD array of high-performance digital signal processing chips that communicate via a flexible, modular message-passing network. The dual-capability architecture is much more effective than a solely SIMD or MIMD organization. The highest level comprises an array of general-purpose microprocessors for symbol manipulation. The first- and second-generation implementations of the IUA architecture are described.>

A collection of routing algorithms for the content-addressable array parallel processor (CAAPP) which allow many more classes of interprocessor communication to be executed efficiently than otherwise on machines with conventional mesh-connected topologies is presented. It is shown that routing on the CAAPP can be executed with simplicity and performance similar to that of a dedicated routing network. Experimental results are presented from random permutations as well as from several common machine vision applications.>

An efficient parallel processing algorithm for detecting straight lines on a mesh-connected computer enhanced with a gate-connection network (GCN) is presented. The algorithm is composed of a modified Hough transform that projects compressed pixels in parallel in a given direction and a parallel procedure that extracts the beginning and end points of detected lines. Both parts require the flexible communication capabilities of the enhance mesh. The GCN can be used to dynamically reconfigure the interconnections between hundreds of processors. It is shown how the GCN can electrically connect all of the edge pixels on a straight line. For an n*n pixel array, the algorithm can detect all lines in O(log n) time. Initial experimental results obtained using a simulator of the GCN implemented on a very-large-scale integration (VLSI) chip are presented. Though the accuracy of the algorithm depends largely on the assigned threshold values, the authors believe its speed is superior to that of any other Hough-based technique by a factor of at least two orders of magnitude.>

First- and second-generation implementations of an image understanding architecture, IUA, are described. The IUA system is designed specifically for computer vision processing that relies heavily on artificial intelligence techniques to classify objects. To provide for low-, intermediate-, and high-level computer vision processing-required for model-/knowledge-based interpretation of sensor data-the IUA system combines three heterogeneous levels of parallelism with associative processing mechanisms. The tightly coupled symbolic and numeric processing capabilities constitute a unique computing paradigm ideally suited to computer vision applications, which require both control- and data-parallel processing. The IUA architecture, hardware, and software are described.>

Architectural research in support of knowledge-based computer vision is described. Efforts are focused on two major areas: the development of the image understanding architecture (IUA) and the benchmarking of parallel processors for vision. Two aspects of the IUA research are discussed. One is the development of the low-level processor chip, which integrates 64 one-bit (serial) processors, data caches, a communication network, and parallel interfaces to image input/output (I/O) hardware and the intermediate-level processors. The other is the ICAP, which is designed to manipulate tokens (symbolic descriptions of extracted image events and their associated attributes) at the intermediate level and to support database functions that allow access to these tokens. Work on an image understanding work bench is briefly described.>

A precision digital edge-line-detection method is presented that was developed for extracting edge contours of resist lines of submicrometer width as imaged by scanning electron microscopy, as a means of inspection in integrated circuit fabrication. The method is based on a modification of the Hough transform.>

The problem of speedily and reliably interpreting range data for industrial object recognition is becoming critically important in the field of robotics and computer vision. This paper presents one approach to attack this problem. It attempts to perform as much classification analysis as possible during the off-line learning process, while only a very small subset of the range data needs to be processed for the on-line recognition. An adaptive matched filter is developed to extract an object's surface feature vectors using range measurement and surface normals. A sparse representation for each object category j is constructed for classification purpose in the form of a Rj-table of selected feature vectors. The approach, based on the concept of the generalized Hough Transform, classifies an object by examining the maximum votes which it receives from various Ri-tables. An optimal selection rule is established for minimizing the misclassification probability. An experiment with a set of simulated range images of nine categories demonstrated the success of the proposed methodology.

This paper presents our progress on automated inspection of VLSI resist patterns as imaged by scanning electron microscopy. A precision digital edge line detection method has been developed for extracting edge contours of resist lines of submicron width, which are crucial for micro registration and detection of defects including bubbles and holes, resist stringers and resist edge defects.