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John D. Provence

dblp:75/6603 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2Databases, data management, data science and information retrieval · 2Systems, architecture and hardware · 1Computer networks · 1 · 1 first-authorTheory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 72% Hardware accelerators and domain-specific architectures · 14% Integrated circuit design · 14%
Computer networks
1 paper
Physical-layer communications · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware description language
0.011995
Measures of Syntactic Complexity for Modeling Behavioral VHDL · DAC 1995
Electronic design automation › hardware description language
VHDL
0.011995
Measures of Syntactic Complexity for Modeling Behavioral VHDL · DAC 1995
Hardware accelerators and domain-specific architectures
systolic array
0.011988
Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel · IEEE Trans. Commun. 1988
Integrated circuit design › digital signal processing circuits
viterbi processor
0.011988
Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel · IEEE Trans. Commun. 1988
Physical-layer communications
channel coding and estimation
0.011988
Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel · IEEE Trans. Commun. 1988
Physical-layer communications › channel coding › convolutional decoding
viterbi decoding
0.011988
Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel · IEEE Trans. Commun. 1988

Methods — techniques the papers use, named apart from their topics

syntactic complexity metrics · 0.0nearest-neighbor data flow · 0.0branch metric computation · 0.0
YearPublicationVenuePosition
1995 Measures of Syntactic Complexity for Modeling Behavioral VHDL
abstract
Article Free Access Share on Measures of syntactic complexity for modeling behavioral VHDL Authors: Neal S. Stollon DSC Communications Corporation, Dallas, Texas DSC Communications Corporation, Dallas, TexasView Profile , John D. Provence Southern Methodist University, Electrical Engineering Dept., Dallas, Texas Southern Methodist University, Electrical Engineering Dept., Dallas, TexasView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 684–689https://doi.org/10.1145/217474.217611Published:01 January 1995Publication History 1citation307DownloadsMetricsTotal Citations1Total Downloads307Last 12 Months2Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
Neal S. Stollon, John D. Provence
DAC2
1993 Control of dynamic systems using fuzzy logic and neural networks
abstract
The use of artificial neural network is proposed for high-speed processing of rules in fuzzy logic controller (FLC). the logic element of an FLC is replaced by a single hidden layer feedforward network. the input and output fuzzy subsets are expressed it of numerical patterns. the network is trained using the back-propagation algori to establish fuzzy associations between the input and output fuzzy subsets. the inference mechanism of the network is compared with that of compositional law of inference. In the proposed implementation of FLC, all the rules are processed in paralle. This implementation has potential for high-speed processing of rules if the network is realized in hardware. the use of neural networks in fuzzy logic self-organizing is also ivestigated. © 1993 John Wiley & Sons, Inc.
Ajay Patrikar, John D. Provence
Int. J. Intell. Syst.2
1991 An Integrated Approach to Routing and Via Minimization
D. Sreenivasa Rao, John D. Provence
Inf. Process. Lett.2
1990 A self-organizing controller for dynamic processes using neural networks
abstract
The use of multilayer feedforward neural networks for self-organizing control of poorly defined dynamic processes is proposed. The control policy at any stage can be expressed in terms of linguistic control rules. These rules are treated quantitatively using fuzzy logic theory and implemented through neural networks to obtain deterministic control actions. The performance of the controller is evaluated at each time step using a performance measure, and the rules which contributed to previous control actions are reinforced. The neural network is then trained using backpropagation to accommodate such reinforcement in controller output. The performance of these controllers was tested through simulation on a number of linear dynamical systems as well as on nonlinear systems such as the cart-pole balancing problem. The results indicate that the controller has strong adaptive properties, and it can be built with only a little knowledge about the system dynamics. The performance of the controller was also observed to be highly robust to system parameter changes
Ajay Patrikar, John D. Provence
IJCNN2
1988 Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel
abstract
The theory and design of systolic arrays for Viterbi processing in communication systems with a time-dispersive time-varying channel is discussed. The architecture, algorithms, and processor elements, for a two-dimensional systolic array are described. The array supports the branch metric computations required for an adaptive Viterbi processor. The array is designed so that computations propagate along the rows of the array, while data symbols propagate along the columns. All interprocessor data flow and connections within the array are nearest-neighbor. The array illustrates how the Viterbi-processor algorithms can be structured to achieve a high degree of computational concurrency. Variations in the array design are described and evaluated in terms of computational resource requirements and utilization and computational throughput. A high-bandwidth memory interface is proposed, and system design considerations are discussed.>
John D. Provence, Someshwar C. Gupta
IEEE Trans. Commun.1